ZX Spectrum Expansion Bus Signals

You and Your SPECTRUM

Many of you reading this would surely like to do something different with your SPECCY. In this article I’ll show you what you can do with your little computer, and how.

First, a brief look at what’s on the bus:

(A line above a signal means that its active state is low.)

********************************
*No.* Top          * Bottom    *
********************************
*1. * FREE         * A11       *
*   *              *           *
*2. * A10          * A9        *
*   *              * ------    *
*3. * A8           * BUSACK    *
*   * ----         * -----     *
*4. * RFSH         * ROMCS     *
*   * --           *           *
*5. * M1           * A4        *
*   *              *           *
*6. * -12V(NOTE)   * A5        *
*   *              *           *
*7. * +12V(NOTE)   * A6        *
*   *              *           *
*8. * WAIT         * A7        *
*   *              * -----     *
*9. * -5V          * RESET     *
*   * --           * -----     *
*10.* WR           * BUSRQ     *
*   * --           *           *
*11.* RD           * U(NOTE)   *
*   * ----         *           *
*12.* IORQ         * V(NOTE)   *
*   * ----         *           *
*13.* MREQ         * Y(NOTE)   *
*   * ----         *           *
*14.* HALT         * VIDEO(NOTE)*
*   * ---          *           *
*15.* NMI          * GND       *
*   * ---          * -----     *
*16.* INT          * IORQE     *
*   *              *           *
*17.* D4           * A3        *
*   *              *           *
*18.* D3           * A2        *
*   *              *           *
*19.* D5           * A1        *
*   *              *           *
*20.* D6           * A0        *
*   *              *           *
*21.* D2           * CK        *
*   *              *           *
*22.* D1           * GND       *
*   *              *           *
*23.* D0           * GND
           GAP
*24.* FREE         * +9V(NOTE) *
*   *              *           *
*25.* D7           * +5V       *
*   *              *           *
*26.* A13          * A12       *
*   *              *           *
*27.* A15          * A14       *
********************************

Signals marked NOTE may not be present on some models (best to check).

This description should be copied out and hung above your bed.

And now, a description of the Z80 pins on the edge connector. It may be a bit too difficult, but I couldn’t explain it more simply.

A0–A15 — Address bus.
Through the address bus, the processor supplies the address of a memory cell or a port number. Remember that the port number is transmitted on the lower eight bits of the address bus.

D0–D7 — Processor data bus. Using this bus, the processor sends or receives data from memory or ports.

M1 — Signal indicating an instruction-fetch cycle by the Z80.

Every instruction cycle begins with an instruction being fetched from memory. During the instruction-fetch cycle, the signal

M1 = 0

is generated, distinguishing this cycle from other processor cycles. During clock states T2 and T3 of this cycle, the contents of the program counter PC are sent along the address bus. The following signals then appear:

MREQ = 0
RD   = 0

Their purpose is to connect memory to the data bus. The processor reads data from the data bus as it transitions from T2 to T3. During clock states T3 and T4, the fetched instruction is decoded and possibly executed (if it does not require additional accesses to memory or a port). During these clock states, dynamic memory is also refreshed by means of the following signals:

RFSH = 0
MREQ = 0

The contents of register R are also placed on bits 0–6 of the address bus.

When the next bytes of an instruction are fetched, or while an instruction is being executed, information is read from or written to memory. Read and write cycles consist of three clock states.

During clock state T1 of a read cycle, the processor generates the signals:

A0–A15 = memory address
MREQ   = 0
RD     = 0

During clock state T2, the output states remain unchanged. In the first half of clock state T3, the processor reads data from the data bus; in the second half of that clock state, it stops generating the signals:

MREQ and RD

During clock state T1 of a write cycle, the processor generates the signals:

A0–A15 = memory address
MREQ   = 0
D0–D7  = output data

In the second half of clock state T2, the processor generates the signal:

RD = 0

During clock state T3, the processor stops generating the signals:

MREQ and WR

An input-output instruction execution cycle differs from a read or write cycle in that, instead of the signal

MREQ

the signal

IORQ

is generated, and a wait cycle is automatically inserted between clock states T2 and T3.

MREQ — Output signal indicating that a memory address is being transmitted on the address bus.

IORQ — Output signal indicating that a port address is being transmitted on the lower byte of the address bus.

RD (ReaD) — Output signal indicating a read from memory or a port.

WR (WRite) — Output signal indicating a write to memory or a port.

BUSRQ — Input signal requesting that the processor release the buses.

If memory is used by more than just the processor, then when another device wants to read something from memory, it must have a “free” bus. To do this, it must generate the signal

BUSRQ = 0

when it wants to perform some operation on memory. The processor reads this input during the last clock state of an instruction cycle. If—

When BUSRQ = 0, the processor places the bus in a high-impedance state and generates the BUSAK = 0 signal. The state of the BUSRQ input is checked on every clock cycle, and when it reaches 1 again, the processor clears the acknowledgement signal and resumes the instruction cycle.

That’s all for now. To be continued in the second part...

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