You and Your Spectrum, Part 2: Z80 Signals and Interrupts

INT — Maskable interrupt request input

At the last clock pulse of each machine cycle, after checking the bus request signal, the microprocessor checks the state of the /INT input. If the interrupt system is enabled (IFF = 1) and /INT = 0, the microprocessor performs a modified opcode-fetch cycle. Instead of /MREQ, it generates /IORQ, and it also automatically inserts two wait states between T2 and T3. Since no /RD signal is generated, none of the input devices can send information over the data bus.

The Z80 microprocessor does not generate an interrupt-acknowledge signal directly: it is obtained by logically ANDing /M1 and /IORQ. On the ZX SPECTRUM edge connector, this signal is labelled /IORQE.

There are three interrupt modes. The /RESET signal sets mode 0. The following instructions change the mode:

• IM 0 — mode 0
• IM 1 — mode 1
• IM 2 — mode 2

In mode 0, an interrupt is accepted as follows: the interrupt-acknowledge signal causes the external device to place the appropriate instruction on the address bus.

In mode 1, the microprocessor automatically jumps to the subroutine located at 38 hex (56 dec).

In mode 2, before selecting this mode, you must place an interrupt-handler jump table in memory. The memory area containing this table is determined by the contents of the eight-bit I register. This register holds the eight most significant bits of the jump-table address. The interrupt-acknowledge signal causes the external device to place the eight least significant address bits on the data bus. Combining the contents of the I register with the address supplied by the interrupt source gives the address of the start of the interrupt-handling routine. Thus, accepting an /INT interrupt in mode 2 involves:

• saving the contents of PC;
• clearing the IFF flip-flop;
• loading the address of the start of the interrupt handler into PC.

The /RESET signal clears the I register, while LD I,A loads the contents of the accumulator into I. The reverse operation is performed by LD A,I.

Whether an /INT interrupt is accepted depends on the state of the interrupt flip-flop IFF. Its state can be changed with the EI instruction (enable interrupts) and the DI instruction (disable interrupts). It is cleared by the /RESET signal and when either interrupt is accepted, except for /NMI, which saves the state of the IFF flip-flop in its auxiliary flip-flop. LD A,I copies the state of this flip-flop into the parity flag P/V, while RETN returns from an interrupt and restores the previous state of the IFF interrupt flip-flop.

NMI — Non-maskable interrupt request input

Accepting an /NMI interrupt causes a jump to a subroutine beginning at address 66 Hex (102 Dec). At the same time, the IFF flip-flop is cleared; its previous state is restored by the return-from-interrupt instruction /NMI (RETN).

RESET — Reset input

An input added only to later versions of the Z80 by PENTAGON, PENTAGRAM and NATO. Its significance is so secret that even the oldest people in the village cannot remember it. For more information, contact Pyza, then run to the mountains to escape the KGB. The Editor-in-Chief will bring you the information in his teeth, but will demand 1000 zł for revealing it...

WAIT — Wait-state input

Any number of wait states can be inserted between T2 and T3 of each processor cycle by setting this input low. The processor checks the state of this input during T2, on the falling edge of the clock signal. If /WAIT = 0, the next cycle is a wait state. During that state, the processor checks the /WAIT input again. If /WAIT = 0, the situation repeats. If /WAIT = 1, the processor proceeds to T3. During a wait state, the signals generated by the processor remain unchanged.

HALT — Halt-state signal output

Signals that the processor has entered the halt state (the HALT instruction).

RFSH — Memory refresh signal output

An output used to refresh dynamic memory.

ROMCS — Internal ROM disconnect input

An input signal that disconnects the computer’s internal ROM.

Video and clock signals

• U — red differential signal
• V — blue differential signal
• Y — luminance and synchronisation signal
• VIDEO — composite video signal
• CK — processor clock (generated by the ULA)

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