(C) Matlash Vladislav
I want to share with the reader, I have modified the
scheme IDE-HDD adapter is willing, but not yet decided to
connect a hard drive or CD-ROM and do not wish to bother floppy
disks, and for those whose work involves with large amounts of
information ...
Scheme IDE-HDD adapter
SUS BUS DD1 IDE BUS
D0 D0 2 March DD8 DD0
D0 Q0 D0 17 DD0
D1 D1 May 4 DD9 DD1
D1 Q1 D1 15 DD1
D2 D2 6 July DD10 DD2
D2 Q2 D2 13 DD2
D3 D3 Sept. 8 DD11 DD3
D3 Q3 D3 11 DD3
D4 D4 December 1913 DD12 DD4
D4 Q4 D4 9 DD4
D5 D5 15 14 DD13 DD5
D5 Q5 D5 7 DD5
D6 D6 16 17 DD14 DD6
D6 Q6 D6 5 DD6
D7 D7 19 18 DD15 DD7
D7 Q7 D7 3 DD7
11 CS0 # DD8
A0 C / 4 DD8
A0 IR 1 RWE # DD9
A1 23 OE # o 6 DD9
A1 DD10
A2 8 DD10
A2 DD2 DD11
A3 D0 3 February 1910 DD11 DD8
A3 D0 Q0 DD12
A4 D1 5 April 1912 DD12 DD9
A4 D1 Q1 DD13
A5 D2 6 July 1914 DD10 DD13
A5 D2 Q2 DD14
A6 D3 8 September 1916 DD11 DD14
A6 D3 Q3 DD15
A7 D4 13 December 1918 DD12 DD15
A7 D4 Q4
A8 D5 14 15 DD13 DA0
A8 D5 Q5 35 DA0
D6 17 16 DD14 DA1
M1 # D6 Q6 33 DA1
M1 # D7 18 19 DD15 DA2
IORQ # D7 Q7 36 DA2
IORQ # 11
WR # / C RES #
WR # 1 R & D a RESET #
RD #-oOE # 23 WWE # DIOW #
RD # 23 DIOW #
RESET # WWC # DIOR #
RESET # 25 DIOR #
DD3
D0 February 18 DD0 CS0 #
A0 1 B0 37 CS0 #
+5 V> +5 V D1 17 March DD1 CS1 #
A1 B1 38 CS1 #
GND D2 April 16 DD2
A2 B2
X1 D3 May 15 DD3 22 GND
A3 B3
D4 14 June 1924 DD4 GND
A4 B4
D5 July 13 DD5 19 GND
A5 B5
D6 August 1912 DD6 2 GND
A6 B6
D7 11 September 1926 DD7 GND
A7 B7
January 30 GND
EAB
19 AP
oEO # June 1939 DASP #
- RWW #
X2
DD4
A4 2 March DA0
D0 Q0 1 KATODLED
A5 4 May DA1
D1 Q1 2 ANODLED
A6 6 July DA2
D2 Q2
WR # 9 August DIOW # R1
D3 Q3> +5 V
RD # 13 December DIOR # 300
D4 Q4
RESET # 14 15 RES #
D5 Q5
17 16
D6 Q6
18 19
D7 Q7
11
+5 V
B1
19 "-" "+" R1
(Scale is taken with respect to the tetrad cells 5x5 mm)
Fig. 2. Drawing of the adapter card
After verifying the correctness of the tester
installation of conductors and the absence-circuiting the chip
card is washed of flux under running hot water (if you do not
use rosin) and give it dry.
It should be noted that the termination and closure of the
signals can be not only between the conductors of the board,
and also within chips themselves.
Next, connect the adapter to perform the following steps:
1. Insert the adapter into an available interface
connector on your computer.
2. Connect 40-pin connector
loop drive IDE. The most common errors connecting loops are
coup connector 180 degrees and a lateral or longitudinal
displacement contacts. From these errors, saves the plastic
bezel, surrounding the pegs the best quality
connectors, and key slot. However,
with the keys happen and confusion: it happens,
the connector loop, which has a return key protrusion on the
tail impaled wrong. Then, for the proper connections, this
ledge necessary to cut (it's easier than qualitatively
perekolot connector). I have personally encountered this
problem connecting IDE ribbon cable to the hard drive.
3. Connect the indicator to
hard drive "HDDLED" in the two-pin
connector on the adapter card. Correctly connect the connection
can be during boot Hard drive - in this case the indicator
should be blinking.
To verify the correctness of all
Connection type:
10 PRINT AT 0,0; IN 117; "": GO TO 10
If everything is correct, then after passing the self test
device to the screen should flash the number 80.
This description is for setting up a
short because of the inability to reflect the various faults
and assembly options adapter. It serves as an assembly
algorithm and run, limited only by some
councils.
Software control
For programmatic interaction with
devices connected to the adapter in
free address space of the input / output computer was chosen as
an address range of ports (see Fig. 3), excluding possibility
of overlap already in use Addressing ports. For this has been
done analysis of existing ones, have become standard
addresses of input / output ports as a short (only used for
decryption younger part of the address bus [A7: A0]) so
and addressing long (use the whole
width of address bus [A15: A0]).
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
XXXXXXX nnnnn 0 1 0 1
>
Selection
Adapter
> Select Registers
Devices
> The older part of the address
port
used as a counter
(Contents of Reg. B) B with
using commands or enter
O
Fig. 3. Organization of the port select register IDE devices
Space I / O ports
adapter is chosen so that the ability to use automatic command
I / O MP Z80.
The dignity of their application that
reduced number of processor cycles
(And consequently time) spent
in an exchange transaction with the device, and saves memory
for the driver program. But their use does not restrict the use
of conventional and semi-automatic command input / output,
revealing a cycle of exchange, which is still considerably
increase speed.
; Example sub-sector reading device identification
ORG # C000
INSTL DI
L2 LD A, # FE
IN A, (# 75); registration status CP # 50
JR Z, L1; No error
CALL # 1F54; test pressing BREAK
RET NC
JR L2
L1 LD BC, # FE75
L3 IN A, (C)
RLCA
JR C, L3; wait for the device
LD A, # EC; Team
INC B
OUT (C), A; Command register
DEC B
L5 IN A, (C)
BIT 7, A
JR Z, L4; accepted package of 256 words
CALL # 1F54
RET NC
JR L5; We are waiting for an answer
L4 LD BC, # 0005; registration data
LD HL, 50000; address data reception
XOR A; counter for 256 cycles
L6 INC HL
IND; Reading [D7: D0]
INI; Reading [D15: D8]
INC HL; because bytes is reversed
DEC A
JR NZ, L6
RET; Successful exits
It should be remembered that the appeal to the registers
of the device must be on a full address is A15-A0.
Fragment of reading the data sector in the K-cycles Z80 # of
bytes . . .
LD HL, address buffer 10 March
LD BC, # 0005, Port Address March 10
INIR (INI 256 commands) 21/16 2
INIR (INI 256 commands) 21/16 2
. . . ----- - Total: 10 762 1910
When ring-opening: 8212 518
Fragment recording sector data in the K-cycles Z80 # of bytes
. . .
LD HL, address buffer 10 March
LD BC, # 10 March 0005
XOR A January 4
LOOP INC HL June 1
OUTD February 16
OUTI February 16
INC HL June 1
DEC A Jan. 4
JR NZ, LOOP 12 / July 2
. . . ------Total: 15 331 1916
Address Space I / O ports
When reading the [D7: D0] the principal part
port address even when reading only
data [D15: D8] is not even:
# 05 Data Register
# 15 Register error
# 25 counter register sectors
# 35 Register of sector number
# 45 Register Low Byte cylinder number
# 55 Register High Byte cylinder number
# 65 Register of device numbers and pins
# 75 status register
When recording [D7: D0] the principal part
addresses are not even, when recording data only [D15: D8] is
even:
# 05 Data Register
# 15 Register of properties
# 25 counter register sectors
# 35 Register of sector number
# 45 Register Low Byte cylinder number
# 55 Register High Byte cylinder number
# 65 Register of device numbers and pins
# 75 Command register
# E5 register control device only [D7: D0]
P. S. By bringing the scheme and making sure to
practice in its performance, I tried as much as possible to
describe in detail the principle its work and the technology of
my build.
If anyone can help me
writing a file window HDD-FDD navigator for software potderzhki
scheme or have any questions please contact:
FidoNet: 2:4635 / 99.111
In a letter to state: Vladislav
Email:
Ukraine
18002, Cherkasy
st. Lenina 10, Apt. 6
Matlashu Vladislav
