ZX Hardware: Spectrum 48K
Spectrum 48K Block Diagram
The Spectrum’s electronic circuits can be divided into four major sections: the microprocessor, memory, circuits for communicating with peripheral devices, and the power supply. The memory consists of ROM and two sections of RAM: 16K RAM and 32K RAM (32K RAM is present only in the Spectrum with 48K RAM). A large number of circuits for communicating with peripheral devices are integrated into a single chip—the ULA. Through this chip, the microprocessor communicates with the keyboard, TV screen, speaker, and cassette recorder. The main components are connected by data buses, address buses, and various control lines.
Main Components of the Spectrum 48K
Z80A Microprocessor
The Spectrum’s central processing unit is the 8-bit Z80A microprocessor. It was developed by the American company Zilog by extending Intel’s 8080 microprocessor, increasing the number of instructions it can execute to 158.
All operations performed by the microprocessor are synchronized in time with the clock. This is a rectangular-wave signal with a stable frequency controlled by a quartz crystal. In the Spectrum, the Z80A runs at 3.5 MHz. Other versions of this microprocessor are also available:
The predecessor, the Z80, can run at frequencies of up to 2.5 MHz, while the newer Z80B has an upper limit of 6 MHz.
16K ROM
Data is written to ROM (read-only memory) during manufacture and can no longer be changed. It is not erased when the power supply is disconnected either. The Spectrum’s ROM is a 16K-byte integrated circuit in a 28-pin package. It is made by HITACHI or NEC. System programs are stored in it (programs that enable the computer to be used): the operating system and the BASIC interpreter. ROM occupies addresses from 0 to 16383, which is most convenient because the Z80 begins executing a program from address 0 when switched on.
32K RAM
The Spectrum version with 48K RAM has 12 more integrated circuits than the 16K version: eight memory chips and four logic chips. The memory chips are organized as 32768×1 (with a capacity of 32 kilobytes). The data input and output lines of each chip are connected together and linked to one line of the data bus. All the chips together form a 32K-byte block (32K×8), with addresses from 32768 to 65535.
16K RAM
This group consists of ten integrated circuits: eight memory chips and two multiplexers. Each memory chip has a capacity of 16 Kb (16384×1), and each has its data line connected to one line of the data bus, so together they form 16 Kb of memory (16384×8). The memory cells in the chips are organized into 128 rows and 128 columns.
ULA
The ULA (Uncommitted Logic Array—a collection of logic whose function is selected as needed) is a 40-pin integrated circuit that replaces a large number of smaller logic chips. It was made specially for the Spectrum. The manufacturer is Ferranti. Several versions of this chip have been installed in Spectrums to date.
The ULA reduced the cost and size of the computer.
Its function is to communicate with the input/output devices. The input devices are the keyboard and cassette recorder, while the output devices are the TV screen, speaker, and cassette recorder.
Keyboard (TA)
The Spectrum has 40 keys connected to one another by conductors. There are eight conductors, each connecting five keys in the same row, and five conductors connecting eight keys in the same column. One terminal of each key is connected to a row conductor, and the other to a column conductor. Each column is connected to +5V through a resistor, so that is the voltage on it when it is inactive—that is, when none of the keys connected to it is pressed.
Cassette Recorder (KI)
A cassette recorder is a device used to record data onto tape and load data from tape.
ZX Hardware: Spectrum 48K
More about how it works and its connection to the tape recorder later.
Speaker
The Spectrum does not have a conventional speaker, but an electroacoustic transducer in the form of a round disc. It is mounted on the circuit board at the lower right. The voltage applied to the transducer moves its diaphragm, converting electrical oscillations into sound.
Transducers of this kind are very common in clocks and other electrical devices with alarms.
Video output
The TV ULA produces three video signals: Y is a combination of the luminance (brightness) and picture-synchronisation pulses. U carries information about the difference in intensity between blue and yellow, while V carries information about the difference in intensity between red and yellow.
Fifty times per second, it reads the contents of video memory, whose addresses range from 16384 to 22527 (the display file), and uses this data to generate the signals that produce the picture on the screen. This frequency is high enough that the eye’s persistence of vision prevents any flicker from being noticed. If the microprocessor attempts to communicate with video memory while the picture is being refreshed, the ULA stops it by removing the clock signal.
This affects its operation only as a very brief pause.
Address multiplexers
AD MU AD MU
Address multiplexers provide the connection between 16 KB and 32 KB RAM and the microprocessor, ROM and ULA via the address buses. Both the 16 KB and 32 KB RAM have two multiplexers each.
Read/write control
Reading and writing data on tape is also controlled by control lines and the read/write controller (IC23/24).
Z80A microprocessor
D0 to D7 — data bus, bidirectional lines (inputs or outputs), which can be in a high-impedance state. Data is exchanged between the microprocessor and memory or an input/output unit via these eight pins.
A0 to A15 — address bus, outputs, which can be in a high-impedance state. These 16 pins allow the microprocessor to address 65536 (2^16) memory locations. When communicating directly with input/output units, it uses only A0 to A7, giving 256 different input/output addresses.
MREQ (memory request) — can be in a high-impedance state. MREQ is active when the microprocessor is communicating with memory.
IORQ (input/output request) — output; can be in a high-impedance state. IORQ is active when the microprocessor is communicating with an input/output unit.
HALT — output; its active state (logic zero) indicates that the HALT instruction has been executed. The central processing unit then stops and waits for an interrupt request from another unit, after which it resumes operation.
NMI (non-maskable interrupt) — input. This interrupt request is always accepted; that is, it cannot be masked like INT. When the current instruction has finished, the microprocessor starts executing the program beginning at address 0066h.
INT (interrupt) — input; interrupt request. When a logic zero appears at this input, the microprocessor stops executing the current program and switches to executing another program intended for this purpose. This allows the microprocessor to respond as quickly as possible to external signals, which is very important in some applications.
CLK — input from the ULA, providing a clock frequency of 3.5 MHz.
RD (read) — output; can be in a high-impedance state. The active state (logic zero) on this pin indicates that the central processing unit is reading data from memory or an input/output unit.
ZX Hardware: Spectrum 48K
WR (English: write), output, with tri-state capability. The active state (logic zero) on this pin indicates that the central processing unit is writing data to memory or to an input/output unit.
BUSACK (English: bus acknowledge), output. With a logic zero on this pin, the central processing unit confirms to the unit that made the request that it may take control of the system.
WAIT, input. Slow memory and input/output units signal the microprocessor via a logic zero on this input to wait for a certain time. When a logic one appears again, the microprocessor resumes operation.
BUSREQ (English: bus request), input. Another unit signals via this input, with a logic zero, that it wants to take control of the system.
RESET, input. This signal (active state is logic zero) puts the central processing unit into its initial state.
M1—machine cycle one, output. A logic zero appears on this pin when the microprocessor reads an instruction code from memory. Simultaneous activation of M1 and IORQ indicates that an interrupt request is being acknowledged (interrupt acknowledge cycle).
RFSH (English: refresh), output. Dynamic RAM, such as the kind used in the Spectrum, must be refreshed at least once every 2 ms to prevent its contents from being erased. The active state of this pin (logic zero) indicates that the address required for refreshing the memory is present on the lower seven bits of the address bus (A0–A6).
ROM D0–D7, eight outputs, data bus. Data from the addressed memory location reaches the central processing unit via the data bus.
A0–A13, 14 inputs, address lines. The microprocessor uses these to address a specific memory location.
E (enable), an input that also serves to activate the chip. It is connected to the MREQ output on the CPU, which indicates that communication is with memory rather than an input/output unit.
OE (output enable), input, enables the outputs. It allows data from the addressed location to reach the data bus through the interface circuit. It is connected to RD on the CPU.
ROMCS ULA 34 R33 680CE (chip enable), input for activating the chip. It is connected via a 680-ohm resistor to the corresponding output on the ULA, which is activated when data is read from ROM—that is, when address lines A14 and A15 are at logic zero. The CE pin is connected to the ROMCS (ROM chip select) connector on the rear of the Spectrum. When this is connected to +5V, the ULA can no longer activate the ROM. The 680-ohm resistor permits this because it prevents the ULA output from being overloaded by this short circuit. This allows us to connect other memory—RAM, ROM, or EPROM—which will be addressed in this address space.
32K RAM 74LS157 (IC26)
A0 A15 CAS RAS WR RD MREQ
IC23a IC23b WRHere too, the address is multiplexed to reduce the number of pins.
When the select signal (S) is at logic one, the two multiplexers (74LS157) place addresses A0 to A7 on the chip’s address lines; when it is at logic zero, they place addresses A8 to A14 on them.
ZX Hardware: Spectrum 48K
The RAS and CAS control signals in this case are generated not by the ULA, but by several logic gates. They are housed in two integrated circuits: the 74LS00 contains four NAND gates (two are used), while the 74LS32 contains four OR gates. The RAS signal for the memory chips is MREQ, slightly delayed by gate IC23a. The multiplexer’s S signal is obtained by delaying RAS with resistor R71 and capacitor C63. Its generation is disabled by IC23c unless either WR or RD is active. CAS is activated by the S signal, delayed by resistor R70 and capacitor C64, and deactivated along with RAS by OR gate IC23b.
When RAS is activated (goes low), the memory chips latch address A0–A7. S then goes low and supplies the chips with addresses A8–A14, which are latched when the CAS signal is activated. If WR is also activated along with RAS and CAS, the memory chips store the data from the data bus at the addressed location. If RAS and CAS are activated while WR is inactive (logic high), the memory chips interpret this as a read operation and place the data from the addressed location on the data bus. During memory refresh, only MREQ—and therefore RAS—is activated; the other signals remain inactive. Addresses A0–A6 are applied to the chip address lines (with S at logic high) for memory refresh.
16K RAM
WR CAS RAS RFSH
74LS157 (IC26)
A0 A13 D0 D7
DRAM A0 DRAM A6The number of pins on this integrated circuit is reduced by multiplexing the address: one part of the address is applied to it first, followed by the other part.
In this case, the chip’s seven address lines are connected to the outputs of a multiplexer (74LS157), whose inputs are connected to the address bus. The RAS (row address strobe) and CAS (column address strobe) signals, generated by the ULA, control the loading of the required address into memory. When RAS appears, the multiplexer transfers the row address from lines A0–A6 of the address bus to the memory chips. When CAS appears, the column address from lines A7–A13 reaches the chips. The memory chips’ address lines are connected to the multiplexer outputs through 330-ohm resistors, and directly to the address lines coming from the ULA (DRAM A0–DRAM A6). This ensures that the ULA has priority over the microprocessor, which is necessary for refreshing the image on the TV screen.
ULA D0–D7: Eight data-bus input/output pins.
DRAM A0–DRAM A6: Seven input/output pins connected to the corresponding address pins of the first 16K of RAM.
Through these pins, the ULA receives information about the address selected by the microprocessor. When refreshing the image, it uses them to address the part of memory containing the required information. At that time it has priority over the microprocessor, because the address from the microprocessor is supplied through 330-ohm resistors.
KBD-9 to KBD-13: Five inputs from the keyboard.
U: Video colour output; the difference between the intensities of blue and yellow.
V: Video colour output; the difference between the intensities of red and yellow.
Y: Video output; luminance and synchronisation.
INT: Output connected to the corresponding input on the microprocessor. The ULA activates it every 20 ms, interrupting the program being executed by the microprocessor and transferring control to the interrupt routine. That routine reads the keyboard state and increments the system variable FRAMES by one.
RD: Input connected to the corresponding microprocessor output. It is active when the microprocessor reads data from memory or an input/output unit.
WR: Input connected to the corresponding microprocessor output. When active, the microprocessor writes data to memory or an input/output unit.
XTAL, input: The quartz crystal connected to this pin controls the frequency of the 14 MHz oscillator located in the ULA.
Dividing this frequency by two gives the 7 MHz required to generate the picture; dividing it by two again gives the 3.5 MHz signal used as the microprocessor clock.
MREQ, input: Connected to the corresponding output of the microprocessor. It is active when the microprocessor communicates with memory.
A14–A15, inputs: Address bus lines. The ULA uses them to identify which part of memory is being accessed: ROM (addresses 0 to 16383), the first 16K of RAM (16384–32767), or the next 32K of RAM.
RAS (row address strobe), output: Active when the first 16K of RAM needs to load row addresses (A0–A6). It is connected via a 330-ohm resistor (R57) to the microprocessor’s RFSH output, allowing it to refresh memory during the 5 ms vertical synchronisation pulse. Otherwise, the ULA refreshes this memory by reading picture data.
ROMCS, output: Connected to the ROM’s CS input via a 680-ohm resistor (R33). The ULA activates it when A14 and A15 are at logical zero, i.e. when data is being read from ROM. CS is connected to the ROMCS pin on the connector at the back of the Spectrum. Connecting it to +5V prevents ROM selection (activation) and allows other memory to be connected in that address space.
IORQGE IORQ R27 680 ohmsIORQGE, input: Connected to the microprocessor’s IORQ output via a 680-ohm resistor (R27), and connected to the pins on the connector at the back of the Spectrum.
Connecting it to +5V prevents the microprocessor from communicating with input/output devices through the ULA, allowing other input/output devices to be connected instead.
CLK, output: Provides a 3.5 MHz clock for the central processing unit. The next diagram shows the position of the cassette input/output and speaker.
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