(C) 1998 by Mr.Beeper
Music by Ironman
Time Management (work with interruptions)
Interrupts can be rightfully attributed to the
the most powerful and interesting resources
computer. Unfortunately, work with them from
BASIC is absolutely impossible and that
so the question for many of you
may be totally new and unknown. By now you may have already
must be sufficiently familiar with assembler, and we hope a
good idea how a microprocessor works, which enables us to
understand that there will be nizheperecheslyatsya. To begin to
figure out what represent an interruption. Try,
Without going into details of design,
explain how this phenomenon is simply "to
fingers. "When you're in the editor
BASIC or TASM and reflect on the next line of the program, the
computer does not rush you, and patiently waits for that a
cluster of Vichy. It may even seem The processor at this time
and does not work. But, as you know, it's not. Just running a
separate part of the program, a similar procedure WAIT: in
tsykle queried by the system variable and LAST_K
when you press a certain key code
it appears in cell 23560. But the question is, where he's from?
Program it is only reading its value, no
modifying its content zhimoe. A permitted
The riddle is quite simple. The fact is
that 50 times a second processor is distracted
from the main program and switched to
implementation of special procedures for handling
Interrupt rasspolozhennoy at 56,
seemed to have met the team RST 56 or CALL
56, only a transition, this is not software and hardware
solution. In the procedure 56, there are two main problems: a
survey keyboard and change the current timer value (the
variable system FRAMES - 23672 / 73 / 74). Key results of the
survey also recorded in the area of system variables
In particular, the code key that was pressed is placed in
LAST_K. After exiting the interrupt processor as if nothing had
happened continues to perform the basic program. The result is
a pretty interestny effect: it seems as if there are two
parallel processors, each of which performs no matter the task.
Everything is fine, but what benefit for
ourselves, we can draw from this? After the ROM
will not change anything. Indeed, interruption of the
programmers would not have been a lot of ku, if it was
impossible to override address of a procedure for handling
them. We have already talked about the existence of the
register I, called the Register of interrupt vectors, and now
describe the role that it performs in programs that use their
own interrupt.
First of all you need to know that there
there exist three different modes of interruption. They
denoted by numbers from 0 to 2.Standartny
mode is 1, and about him we have something
said. Zero mode is not interesting to us,
because in practice it is no different from the first (that is,
in practice, because in reality there are differences, but the
ZX-Spectrum, they not implemented). But on the second mode
need to talk more thoroughly. First, let us say a few words
about how he works and what happens in
computer. With the arrival of the interrupt signal
processor determines the address of a pointer to
procedure interrupt handling. It is of bytes read from the data
bus (Jr.), who, in fact, calls
Xia <vector interrupt> and the contents of the register I (byte
addresses). Then, on address bus override the floor
chennogo pointer, but previously former state address bus is
stored in a stack Thus, the action takes place, similar to the
processor Kamanda CALL. Since the interrupt vector SPECCY
usually 255, in practice, the address pointer
can only be specified registrm I. For
that its value should be multiplied by 256
add 255. To install the new interrupt handler equations,
perform a number of action. Pereches define them in the order in
they should be made:
1. Disable interrupts, as there are ve
probability that the signal will interrupt during installation,
and this can lead Tee to undesirable consequences. Reaches
Xia is executing a command processor DI.
2. Write to memory is nice and advance address pointer to the
procedure of processing Key interrupt (ie the address of this
procedure).
3. Set in the register interrupt vectors
I byte address pointer processing
snip.
4. Set command IM 2 second mode
interrupts.
5. Re-enable interrupts team
EI.
Of course, that by this time, she
procedure interrupt handling must be
Camping in the memory. To return to the standard
mode interrupt to perform similar steps:
1. Disable interrupts.
2. It will not hurt to recover the value of the register I,
writing in his number 63
3. Appoint a team of IM 1, the first mode
interrupts.
4. Enable interrupts.
Several details need to stop
the second and third paragraphs setting interrupts. Assume that
the procedure handler is located at 60000 (# EA60) and memory,
beginning with 65000, no program not used. Means the pointer
can be place just in this area. To Register
I in this case, you can choose one of two
value * eny: 253 or 254. Then, to accommodate the pointer can
be used either Adre sa 65023/65024 (253 * 256 +255 / 256) or
65279/65280 (254 * 256 +255 / 256). For example,
at I equal to 254 write to the address 65279
low byte address of the handler - # 60, and in
65280 put the byte - # EA. However,
be aware that some external
device can change the value of the vector
interrupts. In addition, if your SPECCY
actuated not too good faith
manufacturer, the interrupt vector can sometimes skip a
completely arbitrary and unpredictable ways. Taking this into
attention, even in many branded games
used a slightly different approach. Instead of
write two bytes at a specified address
builds up an entire table size as
minimum of 257 bytes so as to
for any value of the interrupt vector is read the same address.
It is clear that for this table all the bytes have to be
identical. This somewhat complicates the installation of
interruption and require more memory but significantly
increases the reliability of the program.
The most successful for such a table is 255 bytes (# FF). In
this case, interrupt handler must be located on
at 65,535 (# FFFF). At first glance it might seem a strange
choice of this address, because is just one byte! But this
single byte is sufficient if it rewrite the code commands holes
JR. The next byte, located at 0, will indicate the relative
shift of the transition. For zero address in the ROM is written
command code DI (# F3), so completely to Manda looks like JR
65524. Next in the cell can accommodate 65,524 more than
'Long' command and JP addres specified in
her address can be completely arbitrary.
A sample setup interrupt routines:
INT LD A, 24; command code JR
LD (# FFFF), A
LD A, 195; instruction code JP
LD (65524), A
LD (65525), HL; in HL-mail processing
; Chica interrupt
LD HL, # FE00; construction table
LD DE, # FE01; for vectors of the prairies.
LD BC, 256; size tabl.minus 1
LD (HL), # FF; jump address # FFFF
LD A, H; remember senior
; Byte of the address table
LDIR; fill the table
DI; prohibit the prairies. on
; The installation of the second
; Rogo regime prairies.
LD I, A; ask in case I
, High byte address
; Table for vectors
The pit interrupt
IM 2; incl. second mode
EI; permit. prairie.
RET
Before resorting to it in the register pair HL is necessary
to specify the address corresponding yuschey procedures for
handling interrupts. Note that in the memory area starting at
address 65024, to change that - or is not desirable.
If you still need arises,
first make sure that their actions you
do not touch vystanovlennye procedure bye
you. Sub-recovery first
mode looks much easier and in the comments are no longer needed:
INT2 DI
LD A, 63
LD I, A
IM 1
EI
RET
In drawing up procedures for handling interrupts must adhere
to certain rules. First, you wrote podprog
Ramm should be done in a relatively short period of time. It is
desirable that its performance was comparable to
"Pulse" of the interrupt, ie that its derivative
duration did not exceed 1 / 50 seconds.
This rule is not optional, but in
Otherwise, it will be difficult to get the effect of "parallel"
processors. Second, it is absolutely necessary for all re
Giustra, who can change their the value of your procedure
should be saved and restored at the entrance to the
output. This also applies to any variable used not only to
interrupt, but in the main program. In connection with the This
is not recommended is recommended to contact ROM routines, at
least until As long as you do not know exactly what they use
registers and What are the system variables at the same time can
izmeneny.Vyzov be under the program ROM is not
desirable and also because some of
They are allowed to interrupt, which is quite
is not permissible, to avoid recursion (ie,
samovyzova) handler, which should tory
work with interruptions prohibited. However, use the DI at the
start of the procedure is not necessary, as this action is
performed automatically and you only need to take care of
resolving interrupts before exiting.
If you do not want to lose opportunities
provides a standard procedure interrupt handling, can complete
its sub-team JP 56. And when using interrupts in BASIC programs
without this just can not do, otherwise the keyboard
zablokirovana.V will generally formed
botchik interrupt might look like this:
INT PUSH AF
PUSH BC
PUSH DE
PUSH HL
.......
POP HL
POP DE
POP BC
POP AF
JP 1956
In conclusion I would like to invite interestnuyu
progamma, founded on the above prevedennom
text. So, run TASM 4.0 and
"Go for it!
; LOADING WITH MUSIC ON 1 INTERRUPT OF CPU;
ORG # 61A8
DI
CALL # C000; music addres!!!
LD HL, # FD00
LD DE, # FD01
LD BC, # 0100
LD (HL), # FE
LDIR
LD A, # C3
LD (# FEFE), A
LD HL, INT
LD (# FEFF), HL
LD A, # FD
LD I, A
IM 2
EI
CYCL LD B, 53
LD D, TRK
LD E, SEC + 1 ;<<<<<<<< Warning!
LD HL, 26000
CALL LOAD
JR C, CYCL
EXIT DI
LD A, # 3F
LD I, A
IM 1
EI
CALL # C000
RET
INT DI
PUSH HL
PUSH DE
PUSH BC
PUSH AF
PUSH IX
PUSH IY
EX AF, AF '
EXX
PUSH HL
PUSH DE
PUSH BC
PUSH AF
CALL # C006; music addres!!!
POP AF
POP BC
POP DE
POP HL
EXX
EX AF, AF '
POP IY
POP IX
POP AF
POP BC
POP DE
POP HL
EI
JP # 3D2F
LOAD LD (LL62F6), SP
LD A, (# 5CF6)
LD (LL6284), A
LD A, # FB
LD (LL62BD), A
LL6275 LD A, D
AND A
RRA
LD C, # 7F
CALL LL62DC
LD A, # 3C
JR NC, LL6283
LD A, # 2C
LL6283 OR # 00
LL6284 EQU $ -1
LD C, # FF
CALL LL62DC
LD A, # 18
PUSH BC
PUSH DE
LL628E LD BC, # 011F
CALL LL62DC
LD D, A
LD IX, # 20B1
CALL LL62E0
POP DE
POP BC
LL629E PUSH BC
PUSH DE
LD A, E
LD C, # 5F
CALL LL62DC
LL62A6 PUSH HL
LD C, # 1F
LD A, # 80
CALL LL62DC
LD C, # 7F
LD IX, # 3FD5
CALL LL62E0
JP P, LL62F5
CALL LL62E5
LL62BD NOP
POP HL
LD A, (# 5CD6)
OR A
JR NZ, LL62A6
INC H
POP DE
POP BC
BIT 4, E
JR NZ, LL62D1
INC E
DJNZ LL629E
JR LL62D6
LL62D1 LD E, # 01
INC D
DJNZ LL6275
LL62D6 LD (# 6264), DE
AND A
RET
LL62DC LD IX, # 2A53
LL62E0 PUSH IX
JP # 3D2F
LL62E5 XOR A
LD (# 5CD6), A
LD HL, LL628E
PUSH HL
INC A
PUSH AF
LD IX, # 2099
JR LL62E0
LL62F5 LD SP, # 0000
LL62F6 EQU $ -2
SCF
RET
