Shipment memory - memory:
Myths and Realities.
(C) Dr.SQUIZER
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Among novice programmers SPECCY always rumors that someone
managed to transfer the screen faster than
per interrupt. We will understand:
is it possible?
To forward to 6144 bytes
6144 times to perform write cycle in
memory, otherwise it will not be
called the shipment. And how many
Read cycles to execute?
If the image is symmetric or
periodic, then, of course,
less. Leave there room for
creative imagination, and themselves, consider the case of
irregular images.
Remove from the manual in with the e
Team Z80, which include
write operation to RAM:
LD (HL), r LD (ii), r
LD (DE), A LD (nn), A
PUSH qq PUSH ii
LDI LDIR
LD (HL), n LD (ii), n
LD (nn), HL LD (nn), dd
EX (SP), HL EX (SP), ii
LDD LDDR
LD (BC), A LD (nn), ii
For obvious reasons, the list
Not logged command:
INC (HL); DEC (HL); SET b, (HL);
RES b, (HL); same for ii; rotation and shifts (HL) and (ii).
Memory write operations with the help of CALL, RST and
confirmation interrupt leave to cool
jokes.
We now rewrite only those commands that are faster LDIR
(Otherwise, why, and head to fool).
In parentheses indicate the number of CPU cycles to record one
byte in memory with this
Team:
LDIR, LDDR (10.5)
EX (SP), HL (9.5)
LD (HL), r (7)
PUSH qq (5.5)
LD (nn), dd (10)
LD (nn), HL (8)
LD (BC), A (7)
LD (nn), ii (10)
PUSH ii (7.5)
LD (DE), A (7)
Commands such as LD (HL), r is required after a minimum
4-stroke to modify the address. Hence, the actual performance
11 clock cycles per byte. For the same because of rule and EX
(SP), HL. Speed commands LD (nn), dd
and LD (nn), ii so close to LDIR
that the appropriateness of their use for our purposes is
questionable.
But the team LD (nn), HL deserves attention.
The team itself PUSH decrements the address, but sooner or
later require a minimum of LD SP, nn
therefore, its best performance in a loop:
LD SP, nn
PUSH AF
PUSH BC
PUSH DE
PUSH HL
EXX
PUSH BC
PUSH DE
PUSH HL
equal to 6.5 cycles per byte, which
a record for the Z80.
We will not bore readers
similar calculations for the commands to read from memory. We
give the final result:
LDIR (10.5)
LD HL, (nn) (8.0)
POP qq (5.0; 6.0)
This implies that the soft
RAM area can be sent for
is the number of cycles:
LDIR: 6144 * 21 = 129 024
LD HL, (mm)
LD (ss), HL: 6144 * 16 = 98304
POP HL
LD (ss), HL: 6144 * 13 = 79872
POP / PUSH: 6144 * 12.5 = 76 800
As you can see, even at a period
repetition INT in 71,680 cycles
meet in one interrupt is impossible.
Programistskaya same legend was born, apparently of an
incorrect calculation:
POP / PUSH:
6144 * (5.0 + 5.5) = 70 656 (!).
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Shipment memory Memory:
Myths and Realities.
(C) DJNZ
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