INTERRUPTS
(C) Time Keeper
I recently discovered one of the old technical books
information that I have a very
intrigued. What I found there
I say a little later, and remember to start the theory.
Thus, the Z80 processor has two
types of interrupts: maskable
(Int), and Non-maskable (nmi).
After the arrival of the interrupt signal
processor executes the loop
acknowledgment of receipt of interruption during which the bus
Data needed to apply the vector
interrupts. He may have one
of three forms, depending on the
three modes of treatment interruptions, defined by software.
In mode 0, the vector is perceived as a single-byte object
command code, which must be
executed after the interrupt acknowledge cycle. Logic
confirmation interrupt mode 1 believes that after the next
interrupt confirmation command is a command to restart on
address # 0056. If you are using
Mode 1, the interrupt vector is not
needed at all. In some prints indicated that the ZX
Spectrum Mode 0 is similar to mode 1. Generally speaking, it is
not exactly. Ideally, the data bus
Computer tightened to plus "
ie, when reading the interrupt vector data bus contains the
number of # Ff - a native is the team RST # 0056. But this is
only Ideally, in practice it is often
there are computers in which
tire "hangs in the air", ie,
reading vector data bus provides a completely random numbers,
so the replacement regime 1 in mode 0 completely unacceptable!
In mode 2 interrupt vector is interpreted as a junior Byte
Address Table processing interrupts. Significant byte contained
in register I. Together they form the address in the table on
which are taken two bytes of address interrupt handler. Consider
details how to use the second mode preryvavany programs.
Suppose we need "Hang" for interrupting music playback:
ORG # 6101
CALL MUSIC; Initializing music.
DI
LD HL, # 6000; Building a table in memory processing
LD DE, # 6001; interruptions of 256 bytes
LD BC, # 0100, ie taking into account the fact that not
all
LD (HL), # BF; computers have pulled up to "+"
LDIR; data bus.
LD A, # C3; at the address shown in the table
LD (# BFBF), A; ie # BFBF put the command transfer
LD HL, INT_EXE; of the JP INT_EXE.
LD (# BFC0), HL
LD A, # 60; Put I register at the top of the table.
LD I, A
IM 2; includes a second mode, and
EI; allow interrupts.
...
INT_EXE PUSH IX, IY, HL, DE, BC, AF; Actually the program itself
EXX; interrupt handling.
EX AF, AF '
PUSH HL, DE, BC, AF
CALL MUSIC +6
POP AF, BC, DE, HL
EXX
EX AF, AF '
POP AF, BC, HL, DE, IY, IX
EI
RET
In the book, VF Queen "Microprocessor Zilog Z * 80" (from the
series "to assist the developer of microprocessor technology,"
1992. ed. Argus-Master) said
the following:
------------- Cut. ------------
When an interrupt is confirmed in mode 2, the external circuit
should be placed on the data bus
vector interrupt acknowledgment.
Processor unify content
I register with the vector interrupt acknowledgment, creating 16
bit address, which will indicate
corresponding vector addresses
Table interrupt handling.
Since 16-bit addresses can be in memory only in words with even
addresses only Seven of the eight-bit vector
interrupt acknowledgment processor used to generate addresses
in a table, Jr. address bits set to 0.
Thus:
The contents of the vector I with double-byte bus
(As senior + data (as a junior = address table
bytes). bytes with zero processing addresses the Young
PWM bit). interrupts.
------------- Cut. ------------
After reading this book I
was a bit confused.
All written anywhere that is needed to break a plate indicating
at the address in memory, which
Junior and Senior bytes must
match. From reading in the
this book is, generally speaking, that is not so! In the
example above, the plate contains a number # BF, and if you
believe book, address the program interrupt service will be
equal # BFBE. We have the same program is located at # BFBF.
After seeing the contents of the memory cell to I found this at
0. Hence, getting the address # BFBE, processor performs the
first team NOP, and then the program itself, the interrupt
handler. And if at # BFBE will be located, for example, a team
of RST # 00; it will lead to a crash. Topics
at least in this case it runnable.
To make sure I typed program, test for
a scheme formed by address
transition in the parish of interruption:
taking into account the zero bits or without.
Try it on all processors, which were at hand, I got the same
result: the address was formed taking into account the zero
bits. Despite on these results, doubts remain. It says in the
book on the corporate Z-80 (zilog), and among the trusted me
Processors this was not, so for me this remains an open
question, and who knows what other secrets may hold a little
gray box with labeled Z-80 ...
