MPU Z380
[Continued. Previous publications - in numbers 14,12,11,10,
9,8,7].
(C) WLODEK BLACK.
Group instruction multiplication and division.
Mnemonic Meaning Commentary
MLT dd dd <- ddH * ddL "dd" - a pair of registers.
The result of multiplying mlaMLT BC dshego
and senior bytes MLT DE is placed in the same pair.
MLT HL
MLT SP
Team MLT is taken from the instruction Z180 (for
compatibility). It does not affect the flags (!).
MULTW [HL,] pp HL (31-0) <- HL (15-0) * pp (15-0)
The multiplication of words.
"Pp" - a pair of registers.
MULTW [HL,] XY HL (31-0) <- HL (15-0) * XY (15-0)
"XY" - IX or IY.
MULTW [HL,] nn HL (31-0) <- HL (15-0) * nn "nn" - direct
constant-word (which
can be expanded to 24 or 32 bits using
DDIR).
MULTW (XY + d) HL (31-0) <- HL (15-0) * (XY + d)
Multiplication of 16-bit
value pair HL with the word (!) to address (XY + d),
where "d" - shift - can be extended to
words or 24-bit value through DDIR.
MULTUW uu HL (31-0) <- HL (15-0) * uu "uu" - pp, nn, XY, (nn),
(XY + d). Variety
multiply with any addressing mode.
Executed on one clock cycle longer than
with MULTW.
Multiply affect the flags S, Z, C. Flag of the P / V = 0.
DIVUV [HL,] pp HL (15-0) <- HL (31-0) / pp; division 32 times
HL (31-16) <- rest of row-value HL
16-bit Noe value pairs. The remainder is stored in the older
half of the 32-bit pair HL.
DIVUW [HL,] XY HL (15-0) <- HL (31-0) / XY; Same for
HL (31-16) <- remainder. IX, IY.
DIVUW [HL,] nn HL (15-0) <- HL (31-0) / nn; Division
HL (31-16) <- remainder. a constant.
Constant can
be expanded to a 24-or 32-bit through DDIR.
DIVUW [HL,] (XY + d)
HL (15-0) <- HL (31-0) / (XY + d); Division 32-bit.
HL (31-16) <- remainder. HL on the floor (!)
with address (XY + d).
The offset "d" can be extended to 16 or 24
Bit by DDIR.
The influence of the divide on the flags:
S = 0; Z - according to the result; P / V - "V" on the result.
CY is unchanged.
Command group of 8-bit shifts.
It was added not a single new command. The only difference -
the possibility of expanding the displacement "d" to 16 or 24
bits Commands Addressed (XY + d). And another thing: do not
pass the number to the left teams like the RL (IX + d), r (a
shift in the memory cell with simultaneous shipment results in
the register) - These codes are busy other teams.
Command group 16 - and 32-bit shifts.
RLCW pp As RLC, only for couples.
RLCW XY Same for the IX, IY.
RLCW (HL) shift words (!) At (HL).
RLCW (XY + d) A shift of the word (!) At (XY + d).
"D" can be extended through DDIR.
RLW is the same as that similar instructions Z80,
RRCW only for the operand format of the word.
RRW
SLAW
SRAW
SRLW
Impact on the flags similar to the corresponding instructions
Z80.
Group instruction with individual bits.
SET
RES
BIT
Here, all the same. Teams work with the same 8-bit operands, as
in the prototype. The only difference - in operations Addressed
(XY + d) displacement "d" can be extended to 16 or 24 bits
using DDIR. Command group for 16-bit to work with the
individual bits do not exist.
[To be continued].
