Sound on Specki.

* Crossposted in REAL.SPECCY
* Crossposted in FROM_ME

I hit you with my forehead, All!

As I see, the sound card for Spec has interested many. Information on hardware
already appeared, now a few words about programming this feature.

[bite-bite-bite]
Programming.

All ports of the device have the low byte of address #77. The high bytes of the address
are as follows:
DMA controller -
#0C,#1C,#2C,#3C,#4C,#5C,#6C,#7C,#8C,#9C,#AC,#BC,#CC,#DC,#EC,#FC
First timer - #3D,#7D,#BD,#FD
Second timer - #3E,#7E,#BE,#FE
Channel banks - #07,#17,#27,#37
Channel volume - #3F,#7F,#BF,#FF
Interrupt mask - #F7

To work with sound, the controller must be programmed in the
single transmission mode, the transmission priority can be either simple or
cyclic.
Timers set the sampling frequencies of the cancles DMA and interrupts. Channels 1 and 2
timers are clocked at a frequency of 3.5 MHz, and channels 3 at a frequency of 1.75 MHz. Channels 1
and 2 of the first timer set the frequency on DMA channels 1 and 2, channels 1 and 2 of the second
timer set the frequency on DMA channels 3 and 4. All timer channels must operate
in the second mode.
Bank registers set the memory bank with which
exchange will take place. Bank registers contain the most significant bits of the page number, the least significant two bits go to the direct addressaccess. For example, you need to transfer an array, which
is located in page #16 from address #D8E7. The least significant two bits of the page number are %01,
for the DMA address these will be the two most significant bits. Thus we obtain the DMA bank
address
#98E7. The figure illustrates the conversion of page number to address and bank
number for Pentagon-512 and Profi-1024:

Pentagon-512

bits #7DDF Address
╔═І═І═І═І═І═І═І═╗ ╔═І═І═І═І═І═І═І═І═І═І═І═І═І ═І═І═╗
·7│6│5│4│3│2│1│0· bits ·f│e│d│c│b│a│9│8│7│6│5│4│3│2│1│0·
╚І╧І╧═╧═╧═╧І╧І╧Іў ╚═╧═╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧Іў
│ └────┐ │ │ └──────────┒ └────┐ │ ┌┘ └──────────┐ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │
╔═І╧І╧І╧╗ ╔╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧╗
·3│2│1│0· bits ·f│e│d│c│b│a│9│8│7│6│5│4│3│2│1│0·
╚═╧═╧═╧═ў ╚═╧═╧═╧═╧═╧═╧═╧═╧═╧═╧═╧═╧═╧═╧═╧═ў
Bank Address

Profi-1024

#DFFD #7FFD Address
╔═І═І═╗ ╔═І═І═І═І═І═І═І═╗ ╔═І═І═І═І═І═І═І═І═І═І═І═І═І═І═І═╗
·2│1│0· ·7│5│5│4│3│2│1│0· ·f│e│d│c│b│a│9│8│7│6│5│4│3│2│1│0·
╚І╧І╧Іў ╚═╧═╧═╧═╧═╧І╧І╧Іў ╚═╧═╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧Іў
│ │ └────────────┐ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │
│ └────────────┐ │ │ │ └──────┐ │ │ │ │ │ │ │ │ │ │ │ │ │ │
└────────────┐ │ │ │ └──────┐ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │
╔╧І╧І╧І╧╗╔╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧І╧╗
·3│2│1│0· bits ·f│e│d│c│b│a│9│8│7│6│5│4│3│2│1│0·
╚═╧═╧═╧═ў ╚═╧═╧═╧═╧═╧═╧═╧═╧═╧═╧═╧═╧═╧═╧═╧═ў
Bank Address

Fig. Converting a page address to a DMA address

The array cannot cross the boundary of 4 pages, i.e. can be in
#10, #11, #12, #13 pages but cannot be in #13 and #14 pages, such
arrays must be transmitted twice using an end-of-transmission interrupt
or
aligned along the boundary of 4 pages.
Channel volume registers set the volume ranging from 0 (complete
no sound) to 63 (maximum volume). The volume registers are
6 bits wide, so the value of 64 is 0, unlike the Amiga, where 64 is
the maximum volume.
The interrupt controller in the interrupt confirmation cycle issues an interrupt
vector, which indicates which devices have sent an interrupt request.
The interrupt vector has the following structure:

bit 7 - set to 1 if a frame interrupt has arrived, in in the proton
case is reset.
bit 6 - reset to 0 if an interrupt has arrived from the 2nd timer, otherwise
set.
bit 5 - reset to 0 if an interrupt has arrived from the 1st timer, otherwise set.
bit 4 - reset to 0 if an interrupt has arrivedend of transfer on
any DMA channel, otherwise set. In order
to determine which channel has completed transmission, it is necessary to read
the status register of the DMA controller.
bits 3-0 are always set to 1

If several interrupts arrive at the same time, then several bits
are set accordingly independently. For example:

#FF - frame interrupt
#3F - interrupt from the 2nd timer
#5F - interrupt from the 1st timer
#6F - end of transfer interrupt
#BF - frame interrupt and 2nd timer
#EF - frame interrupt and end of transfer interrupt
etc.

Vector #7F does not correspond to any device, but as practice has shown on
an average of once every five minutes such a vector 'slips' and it also needs
to be processed. It corresponds to a frame interrupt, which occurs at the moment
the EI command is executed.
The mask register allows you to mask individual interrupt types. The layout
of bits is as follows:

7 6 5 4 3 2 1 0
╔═І═І═І═І═І═І═І═╗
·x│x│x│x│0│1│1│1·
╚═╧═╧═╧═╧І╧І╧І╧Іў
│ │ │ └─── allows interruption of the end of transmission
│ │ └───── allows interruption of the 1st timer
│ └─────── allows interruption of the 2nd timer
└───────── allows personnelinterrupt

Unlike other interruptions, personnel interrupts are allowed not 1, but 0.

[bite-bite-bite]

That seems to be all for today. Next time I'll tell you about something else.

u pakeda, All, pakeda!

[Team thief Alos MUST DIE!]