SMUC unknown ports

Immediately click on RESET, All!

Below is the breakdown of SMUC ports. The questions indicate ports
of unclear purpose.
The A9 signal is not output to the ISA bus, which also seems strange. It would be nice
if someone
with a real piece of hardware clarified the conditions for sampling the controller (IMHO I entered extra signals there)
and the purpose of unidentified registers.

There are questions: when accessing which ports, the IDE drive registers are read and written --
when accessing the shadow register containing the upper 8 bits of the drive data bus, or when
accessing the low-order part of the data register?

What serial EEPROM chip (connected via I2C, small
such, 8-pins)
is installed in the SMUC controller? 256 bytes or more? There is
an assumption that what is written inside
is the same thing that is written to the 15th sector of the tr-dos disk. That is
autoload can be done
not only from the disk, but directly from the eeprom.

Where is the alarm output (interruption, that is) of the RTC chip (512VI1
aka "CMOS") connected?
To IRQ0 of the interrupt controller? And where are IRQ1,2,3 connected?
Are interrupts (IRQ2-IRQ7) from the ISA slot output somewhere? Must go to the PIC (interrupt controller type 580BH59).

CONTROLLER SELECTION CONDITIONS:
{ a0=0 } AND { a1,a5,a7,a11,a12=1 } AND {trdos active}
|
| ! ISA-BUS ADDRESSES:
| ! a8,a9,a10,a13,a14,a3,a4 isa/ide/pic address (A0-A6)
|
|
+- a6=1 access to ISA slot
| | (!) INFLUENCE OF A13 ON THESE PORTS IS UNKNOWN!
| |
| +- a2=1
| | |
| | |
| | +- a15=1 ??? (ISA A9 ?) UNKNOWN REGISTER
| | | |
| | | +- a13=1 ???
| | | |
| | | +- a13=0 ???
| | |
| | |
| | +- a15=0 isa bus ports rw
| | | isa address bits(A9-A0): (cp==control port bit)
| | | { ? (0), cp.2, cp.1, a4, a3, a14, a13, a10, a9, a8 }
| | |
| | +- a13=1 ???
| | |
| | +- a13=0 ???
| |
| |
| +- a2=0 ???
| |
| +- a15=1 ??? UNKNOWN REGISTERS
| | |
| | +- a13=1 ???
| | |
| | +- a13=1 ???
| |
| +- a15=0 ???
| |
| +- a13=1 ???
| |
| +- a13=0 ???
|
|
+- a6=0 access to SMUC devices
|
|
+- a2=1 access to IDE and PIC controllers
| |
| |
| +- a15=1 ide controller ports
| | |
| | +- a13=1 ide interface registers rw
| ||
| | +- a13=0 shadow ide register rw ?
| |
| |
| +- a15=0 interrupt controller register block rw
| |
| +- a13=1
| | (what is the impact of this bit)
| | (for the work of SMUC and controller)
| +- a13=0 ( interrupts? unknown )
|
|
+- a2=0
|
|
+- a15=1 rtc/control port
| |
| +- a13=1 control port
| | + bit0 isa/pic/ide reset (0 active) wo
| | + bit1 A7 ISA wo
| | + bit2 A8 ISA wo
| | + bit3 enable interrupts from pic (1 active) wo
| | + bit4 SDA out wo
| | + bit5 write protect NVRAM (1 active) wo
| | + bit6 write SCL, read SDA rw
| | + bit7 0=(rtc read, ide command register block),
| | 1=(rtc write, ide status register block) wo
| |
| +- a13=0 rtc port
| control port bit7=0 write address, read data
| control port bit7=1 write data
|
|
+- a15=0 fdd status port rw
+ bit7 1=drive A: real disk, 0=emulated
+ bit6 1=drive B: realdisk, 0=emulated

ro = read only
rw = read and write

ps: port table from Jason I have...