Scheme for replacing ROM with cache (c) ARC

Here, I’m posting a circuit, very, very useful :) ARC invented it after
he was convinced that a similar circuit by Roman Milyukov refused to work for him.

=== Cut ===
REPLACING ROM WITH CACHE
(I did it myself. It works :))
(Scheme supplemented by at the request of the workers (Tigrr's :)))

1533КП12
┌──┬┬──┐
1533ЛЛ1 +5v ──────6┤A0││YA├7─> SL0
┌─┐ /DOS ──╦────5┤A1││ │
DOS BAS ──╦─────│─┤ │ ┌────────│╦│──3┤A3││ │
│ │ ├─┤ │ │││ ├──┤│ │
│ ┌─┐ └─┤1├──┘ +5v ─│││─10┤B0││YB├9─> SL1
╠─┤&O───┤ │ ││└─11┤B1││ │
└─┤ │ └─┘ │└──12┤B2││ │
└─┘ └───13┤B3││ │
1533LA3 ├──┤│ │
KD1 ─────14┤S0││ │
KD2 ──────2┤S1││ │
┌──1OEA││ │
╠─15OEB││ │
│└──┴┴──┘
─┴─
1533КП11
┌──┬┬──┐ ┌─┐
┌──────────2┤A0││Y0├4────────┤1├───> /WRcash
│ KD3 ───3┤B0││ │ /WR ──┤ │
_______ │ ├──┤│ │ └─┘
тpиггеp ──Ў──────────5┤A1││Y1├7──────────────> A14cash
│ SL1 ───6┤B1││ │
│ ┌─┐ ├──┤│ │
└───┤&│ ┤A2││Y2├
┌─┤ O─┐ ┤B2││ │
│ ├─┤ │ ├──┤│ │
SL0 ────╩─┤&│ └─14┤A3││Y3├12────╦────────> /CSrom
SL1 ──────┤ O───13┤B3││ │ │ ┌─┐
└─┘ ├──┤│ │ ╠──┤&O───> /CScash
KD0 ─────────────1┤A ││ │ └──┤ │
┌─15OOE││ │ └─┘
│ └──┴┴──┘
─┴─

1533ИД7 1533ТМ9
┌──┬┬──┐ ┌──┬┬──┐
A12 ──1┤A0││0 O D0 ───3┤D0││Q0├2──> KD0
A13 ──2┤A1││1 O D1 ───4┤D1││Q1├5──> KD1
A14 ──3┤A3││2 O D2 ───6┤D2││Q2├7──> KD2
├──┤│3 OR #CFF7 D3 ──11┤D3││Q3├10─> KD3
A15 ──6┤E2││4 OR11───── ├──┤│ │
A3 ──5OE1││5 OR └─────────9/C ││ │
────O──┌0 #EFF7 ┌──╦─1OR ││ │
┌─┐ │ └──┴┴───┘ │ │ └─────W ─┤1├─┘ ─┴─ █
/IORQ ─┤ │ 0.1mk ─┬─ █ 10k
└─┘ (p
──┘ └──╣
─┴─

DOS (8:dd76) and /DOS (9:DD76) - signals from the BAS drive controller (12:DD62) - 4 bits of popta #7__FFD___br> (8:DD67) - with TM2 tpiggepa cache (generally the LPRINTIII :))

D0-D3, A3, A12-A15 /WR, /IORQ - signals of ppocessopa :)

CSrom - 20 legs of RCD 20 from hook up mikpuhi cache
Ha 22 legs of the mikposche cache send a signal from 22 legs of ROM

Disconnect the backrest from 6 legs of DD66 (LP8)
(or leg from the backrest :)) (you can puke!!! DAHY FOR PEHTAGOH'a 128 !!! )

Spinning toe micposchemes LL1 and LA3:
input 1,2 4,5 9,10 12,13
output 3 6 8 11. Tep

is all. records in popt #CFF7:

Ppi D0 = 0 has 16K cache + replacement of 1 stpany of ROM:

D2 │ D1 │ what_change
│ │ 0 bank cache
────┼────┼──────────────────
0 │ 0 │ do not change anything
0 │ 1 │ Tr-DOS
1 │ 0 │ 128BASIC
1 │ 1 │ 48BASIC

When D0 = 1, 2 ROM pages are replaced:

D2 │ D1 │ what_to_change
│ │ 0 cache bank │ 1 bank cash
────┼────┼────────────┼────────────
0 │ 0 │ nothing │ nothing
0 │ 1 │ Tr-DOS │ 128BASIC
1 │ 0 │ 128BASIC │ 48BASIC
1 │ 1 │ 48BASIC │ Tr-DOS

In mode D0=1: D3=0 - allows writing to the replaced ROM
D3=1 - prohibits writing to the replaced ROM

To replace the ROM you need to:
load images into memory;
write value 5 to port #CFF7;
set the required cache bank in the ROM area with bit 4 of the port #7FFD;
write images to the cache,
by writing to port #CFF7, enable the desired operating mode.

In D0=1 mode, when emulating a ROM, BE SURE to set D3=1!
(ROM for some reason really likes to spoil itself, especially TR-DOS)

I suffered from (c)ARC at the request of Tigrr's :)

Last Edition 04/21/1999 22:30

Appendix I
(Cache trigger circuit)
TM2
┌─┬──┐
A2 ────┐ LL1 /RES ───1OR│ Q├5
LL1 │ ┌─┐ A7 ───2┤D│ │
┌─┐└──┤1├─────────────3/C│ _│ _______
/IORQ ─────┤1├─────┤ │ ┌──╦─╦─4OS│ QO6────> trigger
/RD ─────┤ │ └─┘ │ │ │ └─┴──┘
└─┘ magic+ / │ █ 1k
│ │ │
Everything that hangs on ─┴─ │ o +5v KD522 (521)
4 leg TM2 can not be └─────────┤<├──╦─────────> /NMI
do, and submit +5v 'Old' /NMI ────┼<├──┘ 'New'

Appendix II
(Cache chip pinout)

┌────┬────┐
10│ A0 │ │
9│ A1 │ │
8│ A2 │ │
7│ A3 │ │
6│ A4 │ │
5│ A5 │ │
4│ A6 │ │
3│ A7 │ D0 │11
25│ A8 │ D1 │12
24│ A9 │ D2 │13
21│ A10│ D3 │15
23│ A11│ D4 │16
2│ A12│ D5 │17
26│ A13│ D6 │18
1│ A14│ D7 │19
╞────┤ │
27o WR │ │
20o CS │ │
22o OE │ │
└────┴────┘

Pinout, in general,almost the same as 27512.
The power supply is standard, the 28th leg is +5V, the 14th is ground.
=== Cut ===

Bye, All! Megus/Brainwave^X-Project. [ZX] [NeOS]

28 Apr 99 at 17:38:36 Roman Petrov and All argued
on the topic Scheme for replacing ROM with cache (c) ARC.
I should comment...

My own glitches ;)

RP> Here, I’m posting a diagram, very, very useful :) ARC invented it after then
RP> I was convinced that a similar scheme of Roman Miliukov refused to work for
RP> him.
I didn’t put together Miliukov’s scheme myself, so don’t blame me :)
It didn’t work for another comrade...

RP> 1533ID7 1533TM9
RP> ┌──┬┬──┐ ┌──┬┬──┐
RP> A3 ──5OE1││5 O └────────9/C ││ │
[skip]
RP> ┌─4OE0││6 O9─> #EFF7 ┌──╦─1OR ││ │
RP> ┌─┐ │ └──┴┴──┘ │ │ └──┴┴──┘
RP> /WR ─┤1├─┘ ─┴─ █
RP> /IORQ ─┤ │ 0.1mk ─┬─ █ 10k
RP> └─┘ (approximately)│ │
RP> └──╣
RP> ─┴─
^^^^^^^^^
And here I peed myself :)
The resistor must, of course, be connected to +5v, and the capacitor to ground.
Don’t quibble about the approximate capacitance of the capacitor! :)
Well, I didn’t have anything else ;)

RP> Allwhat hangs on ─┴─ │ o +5v KD522 (521)
RP> 4th leg TM2 can not └─────────┤<├──╦─────────> /NMI
RP> do, and apply +5v 'Old' /NMI ────┼<├──┘ 'New'
^ here is also a 1k resistor at
+5v

With a big “hello”, ARC.