Hard drive problems

After connecting the (hardware) HDD and modifying the ZXNext driver for my
ports, I tried to create a device in IS-DOS (using create.com)
The sector check is successful (bad=0). During the test, you can hear the heads moving inside the HDD. After checking, after a few seconds
returns to create.com. When trying to select a “created” device
it produces errors 86 or 87 (sometimes this is successful, but it is
impossible to write anything there).
Results of “direct” experiments:
The “sleep” command is always executed (even from BASIC).
The numbers that were written there are mainly read from the HDD registers
(cyclic polling from BASIC). Sometimes (about 1 out of 20 times) another number (most often 0) can be read.
The HDD initialization and recalibration commands are completed successfully.
Immediately after issuing the read sector command (#21), the 0th value is setbit
of the status register (error), contains #59. In this case, code #10 is detected in the error register. Each time, similar but
different information is read from the same sector (bytes #00 and #FF predominate). After receiving all the requested
data, the status register contains #51.

What is the problem here? Who knows?

Seagate ST3291A hard drive (was successfully tested on a PC, no problems)

Regards, Sergey Karachentsev.

[Sunday January 30, 2000] at [22:25:00] Sergey Karachentsev wrote a
letter to All.
They discussed the topic “Problems with the hard drive.” Let's continue what we started...

SK> After connecting the (hardware) HDD and redoing the driver
^^^^^^^^^^^^^^^^^^^
SK> ZXNext for your own
^^^^^^^^^^^^^^^
SK> ports
^^^^^
[skip]

SK> What is there a problem here? Who knows?

See the underlined part above. You probably have conflicting input-output ports
of “your” zxnext-controller and something else.
The original zxnext-hdd circuit very much “clogs” the address space of Speck’s input-output.

Before altering the circuit for your own ports, you should have done the following:

- write down ALL _your_ ports on a piece of paper hdd, full 16-bit!

- In basic_48, check them ALL for READING (!) (PRINT IN).

- For all ports #FFh (255) (!) should be read.

Only this can more or less accurately (exceptions are possible: immediately after RESET, #FF are read from
AY ports [#fffd, #bffd]) say about the operation of your device with
independent I/O ports.

Conclusion: disconnect your hdc from the computer buses (you can in the main decoder, replace the signal
/IORQ with log "1"), check what is written above, if not #FF - start
"clearing" the ports foryour
hdc ports.

Best regards, Felix.

[I ZX]

FK> See underlined parts above. You probably have conflicting input/output ports
FK> of “your” zxnext controller and something else.
This is completely excluded! On my PROFI board, only VG93, BB55 and AY-8910 have incomplete (original) decryption, all other ports have 16-bit (!) decryption, all external devices have 8-bit decryption.

FK> The original zxnext-hdd circuit very much “clogs” the address space
FK> input-output Speck.
The ports of my controller are encrypted with all 8 low-order bits of SHA.

FK> You should have done the following before altering the circuit for your ports:
FK> - write down on a piece of paper ALL _your_ hdd ports, full 16-bit!
already done, recorded and printed

FK> - B basic_48 check them ALL for READING (!) (PRINT IN).
already done

FK> - For all ports #FFh (255) (!) should be read.
#FF received everywhere (with no HDD connected)

FK> Only this can more or less accurately (exceptions are possible: immediately after
FK> RESET
FK> from AY ports [#fffd, #bffd] #FF are read) your
FK> device
FK> with independent I/O ports.

FK> Conclusion: disconnect your HDC from the computer buses (you can replace the signal
FK> /IORQ on the main decoder with log "1"), check what is written above, if not #FF -start
FK> "clearing" the ports for your
FK> hdc ports.
When you remove the controller from the slot (the buffer circuit from SPECTRUM EXPERT 2 is assembled)
#FF is always read (except for the internal ports of the board and the ports installed in
peripheral device slots)

The hard drive is fully operational (checked again on the PC)

C Best regards, Sergey Karachentsev.

Once, Thu Feb 03 2000 17:21, Felix Knajzev wrote to Sergey Karachentsev about
[Problems with the hard drive]:

FK> SE2 has now been taken away from me. If *briefly*, then *how* does this “Christmas tree”
FK> provide processor buses for external devices?

It provides it correctly ;)

You need to ask more specifically.

All the best.
Dmitry.

... LD..X-TRADE... [ZX]

02 February 2000 you wrote here:

SK> This is completely excluded! On my PROFI board, only VG93, BB55 and AY-8910 have incomplete (original)
SK> decryption, all other
SK> ports have 16-bit (!) decryption, all external devices have
SK> 8-bit decryption.

IMHO you went too far with the completeness of decryption. :)

SK> When removing the controller from the slot (the buffer circuit from SPECTRUM
SK> EXPERT 2 is assembled), #FF is always read (except for the internal ports of the board and ports

Analyze the timing parameters of the signals in your controller, bugs are somewhere there.

All the best.
Roman.
[ZX]

DL> provides correctly ;)

I have no doubt. ;)

DL> You need to ask more specifically.

Where can you be more specific? :-/

We have a port. :) We want to read/write from/to it. How does the Christmas tree open the buffer (D0-D7)
for him? :) Should the sampling signal of this port be dragged from the decoder of this port to it? Or what? I only had time to briefly look at the diagram. :(

06 Feb 00 03:09, Felix Knajzev wrote to Dmitry Lomov:

FK> We have a port. :) We want to read/write from/to it. How does the Christmas tree buffer
FK> (D0-D7) open for him? :) Should the
FK> sample signal of this port be dragged from the decoder of this port to it? Or what? FK> only had time to look at the diagram briefly. :(

IMHO it opens up for everyone. Whoever is stronger will win ;-(

... no day without speccy!

recording without problems - by default, data, address and control buses are
translated externally. reading: if we have IORQ=0 IOGE=1 RD=0, open the buffer towards the computer (reading the device standing on the tree). if there is BUSAK,
the control changes completely. The address and control go from outside to the computer, and the data
goes depending on the control signals, and reading by the device on the tree of devices both inside the computer and on
the same tree must be processed correctly;)

Does anyone have a description of the electrical parameters of the IDE bus?

Regards, Sergey Karachentsev.

SK>> Assembled buffer circuit from SPECTRUM EXPERT 2
FK> ^^^^^^^^^^^^^^^^^
FK> You forgot to mention this. Do you have anything else
FK> connected to this “tree”?
Only KEMPSTON MOUSE. I tried to disable it.

SK>> it always reads #FF (except for the internal ports of the board and the ports
SK>> installed in the slots of peripheral devices)

FK> So there are two points left:
FK> 1. Error in the driver (you rewrote it, right?)
I just entered my port numbers.

FK> 2. Your hdc does not get along with "Christmas tree".
I think the logic of the hard drive does not get along with the TTL logic of the controller.
Electrical matching is required.
And as luck would have it, I don’t have any information on IDE bus standards :((((((((

FK> SE2 has now been taken away from me. If *briefly*, then *how* is this “Christmas tree”

SK> I just entered my port numbers.

Or maybe the driver is still wrong?

SK> I think the logic of the hard drive does not get along with the TTL logic of the controller.
SK> Electrical matching is required.

There can only be one problem. In a long loop with immeasurable
inductance, the signal “rings”. The screw controller must be assembled on
555 series, do not install 1533 under any circumstances! And you can put a 50 ohm resistor
in each wire.

SK> And as luck would have it, I don’t have any information on IDE bus standards
SK> :(((((((((

This will not help you.

One day, Mon Feb 07 2000 05:42, Kirill Frolov wrote to Sergey Karachentsev about
[Problems with the hard drive]:

SK>> I think the logic of the hard drive does not get along with the TTL logic of the controller.
SK>> Electrical matching is required.

KF> There can only be one problem. In a long loop with immeasurable
KF> inductance, the signal “rings”. The propeller controller must be assembled on
KF> 555 series, do not install 1533 under any circumstances! And in each wire
KF> you can put a 50 ohm resistor in the gap.

with such ends and 1533 will roll. and even, IMHO, it will be better. here without the ends -
yes, 1533 is ringing.

DL> recording without problems - by default, data buses, addresses and
DL> control are translated externally. reading: if we have IORQ=0
DL> IOGE=1 RD=0, open the buffer towards the computer (reading
^^^^^^^^^^
That is, if more than one device is installed in the tree, then the bus
will be received by the one whose IOGE interception circuit works faster?

Maybe the person has a subject because of this?

DL> of the device standing on the tree). if there is BUSAK, the
DL> control changes completely. The address and control go from outside to the computer, and
DL> data goes depending on the control signals, while
DL> the device on the
DL> tree must correctly read devices both inside the computer and on the same tree ;)

Senks. Everything is clear and clear.

I wonder if support for the BUSAK Christmas tree was planned initially or
due to the fact that akasia turned up - AP6 was used for a simpler
wiring? ;)

FK> ^^^^^^^^^^^
FK> Ie. if more than one device is installed in the tree, then the
FK> bus will be received by the one whose IOGE interception circuit works faster?

All at the same time. There are no differences between the slots, they are parallel.
Or am I wrong?

FK> I wonder if support for the BUSAK tree was intended initially or
FK> due to the fact that acasia turned up - AP6 were used for more
FK> simpler wiring? ;)

And I installed IR22 zones...

SK>> SPECTRUM EXPERT 2) always reads #FF (except for internal ports
SK>> board and ports
RM> Analyze the timing parameters of the signals in your controller, bugs
RM> somewhere there.

TRUTH IS OUT THERE... ? (C) X-files.

07 Feb 00 22:25, Dmitry Lomov wrote to Kirill Frolov:

KF>> collect for 555 episodes, do not put 1533 under any circumstances! And in
KF>> you can put each wire with a 50 ohm resistor in a gap.

DL> with such ends and 1533 will roll. and even, IMHO, it will be better. without
DL> ends - yes, 1533 rings.

And I would put a Schmidt trigger in each wire,
it helped with the modem better than resistors...

DL>> without ends - yes, 1533 rings.

KF> And I would put a Schmidt trigger in each wire,
KF> with the modem it helped better than resistors...

oh well, just one glitch was replaced by another, less noticeable ;)

You're saying something wrong.

If two devices recognize their address at the same time, it won't work
at all. all devices after the Christmas tree chips are parallelized, therefore, even in
this case, the data bus will simply open “inward”, and if the devices want to
load each other, that’s their business ;)
the only thing that is flawed is that on the bus _before_ the tree there should be no
devices that form IOGE, just as _after_ the tree there should be no devices
that do not form IOGE. therefore, for example, SMUC can only be turned on before it -
it does not generate IOGE.

SK> IDE bus :((((((((

Actually, you don’t really need this. The main thing for your hdc (and the
hdd interface) is to ensure the build-up of a fairly decent capacitance and inductance of the
interface cable. Any MS TTL buffer, i.e. one that
is capable of transmitting 24 mA (and/or more) for log.0 at the output. As Kirill Frolov already said here, it is not recommended to install the K555 series (I can find the author’s justification Nemo). By the way, I noticed the same point on almost all MIO-ISAs ("isa" cartoon) from the offtopic: buffers for IDEs. 74LS245 (555AP6) and 74LS244 (555AP5).Which MCs do you have the cable loaded on?

+More: Try installing
22...56 Ohm resistors into the gap between contacts 23 and 25 of the ide cable. Install them on the side of the end of the cable
that fits yours. hdc.

08 Feb 00 22:00, Felix Knajzev wrote to Sergey Karachentsev:

FK> interface loop inductance. Any
FK> MS TTL buffer copes with this wonderfully, i.e. one that is capable of delivering 24 mA (and/or more) to
FK> log.0 output. As Kirill Frolov already said here, the optimal
FK> series is the K555 series. It is not recommended to install KR1533 (I can find it

Why isn’t the main unit 155? By the way, 1533 can do it too.
It’s not a matter of the supplied current in static mode, but the design
of the output stages, IMHO.

FK> Does your HDC form IOGE? How does it do it?

And it does necessary?

KF>> And I would put a Schmidt trigger in each wire,
KF>> with the modem it would help better than resistors...

FK> Is the rule like “lots of INI” and “lots of OUTI” still for your new ports
FK>?
Not only INI's and OUTI's but also INIR with OTIR :)

FK> buffers for IDE are 74LS245 (555AP6) and 74LS244 (555AP5).
FK> Which MS do you have the cable loaded on?
Data bus (assembled according to the Sprinter controller circuit):
two K1533AP6 and one K555ИР23
Signals HA0,HA1,HA2: K555LI1
Signals CS0,CS1,IOW,IOR: K1533LL1

FK> +Additionally: Try placing
FK> resistors 22...56 Ohm into the gap between contacts 23 and 25 of the ide cable. Install them on the side of the end of the cable
FK> that fits your hdc.
I tried installing 56 Ohm resistors on all K1533LL1 outputs.
At first glance, everything is OK, sometimes some sectors are read incorrectly.

FK>> faster?

DL> you are saying something wrong.

DL> if two devices simultaneously recognize their address, this
DL> will not work at all. All devices after the Christmas tree
DL> microcircuits are parallelized, therefore, even in this case, the
DL> data bus will simply open “inward”, and if the devices want
DL> to load each other, that’s their business ;)

That’s what I’m talking about. ;)

[skip]

[skip]

FK>> capacitance and inductance of the interface loop.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
KF> Why isn't the line 155?

Yes, for God's sake. Even better. Or 531. :) Powerful!

KF> By the way, 1533 can also
KF> after all.
KF> The point here is not in the current supplied in static mode, but in the
KF> design of the
KF> output stages, IMHO.

See. underlined.

FK>>> Does your hdc form IOGE? How does he do it?
KF>> Is it necessary?

10 Feb 00 11:08, Sergey Karachentsev wrote to Felix Knajzev:

SK> I tried installing 56 Ohm resistors on all K1533LL1 outputs.
SK> At first glance everything is OK, sometimes some sectors are read
SK> incorrectly.

Does it give an error or is it reading garbage from there? How does he write?

I.e. is it better???

SK> some sectors are sometimes read
SK> incorrectly.

FK>> Does your hdc form IOGE? How does he do it?

SK> Forms. I use signals A0...A7 and /M1. The decoder
SK> is built on the IC
SK> K1533LA2, K1533LA4 and K1533ID7.

Which circuit do you use to directly push IOGE into log.1?

Yes, +one more thing: check the power distribution (+5V and common wire) on the hdc board. All
conductors have the largest possible cross-section (thick) and minimum length.
Hang a 0.1 µF ceramic blocking capacitor directly to the MS power terminals (especially AP6 and IR23). Place one electrolyte (preferably
K53 or K52 series) at +5V and a common wire in the place on the hdc board where
power is directly supplied.

Best regards, Felix.

[I ZX]