Help the teapot.

Please tell the teapot. how to connect to the Pentagon
AP-6 for buffering the address bus.

All the best.
Sincerely, Vitaliy.

//The dollar exchange rate in Lisichansk is $5.47 for 1 hryvnia.

And it all started on 02-Jun-00 at 19:49:30, when Vitaliy Gerasin
was talking to All about Help the teapot.

VG> Healthy bulls, All!
bullies, ∙ and let's be healthy! ;)

VG> Tell the teapot plz. how to connect buffering of the address bus to the Pentagon AP-6 on
VG>.

Here you go - here are some pretty smart thoughts on the issue you are interested in.

> beginning ZX_EXTEN.TXT
╔═══════════════════════════ ═══════════════════════╗
║ The ZX-SPECTRUM 48 & 128 computers ║▒
║ --- ║▒
║ * Extended devices and user's manual * ║▒
║ (C) UA3PRQ / Borisov Serge June 1993 ║▒
║ ║▒
╚═══════════════════════════ ═══════════════════════ў▒
▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒ ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒

This information is intended for users
of computers compatible with models from the company "SINCLAIR",
who want to use this most popular machine in our
country not only for games and entertainment, but also
for serious use with various interfaces:
music coprocessor, serial
RS-232 interface, 2716/27512 PROM programmer,
programmable port KR580VV55 and devices
working through it, ADC, DAC, printer and
many others.

Main The problem facing ZX-SPECTRUM
users usually consists of bringing their version of the computer 'up to condition' by introducing various modifications to the circuit for use with other
devices. Most of the circuits of this kind, published in many amateur radio publications, were intended for isolated operation and many simply contradict each other in the principles of connection. This forces users to spend a lot of time on
achieving compatibility between devices; unfortunately, such
experiments are often accompanied by periodic 'burnout' of various parts of the computer circuit and peripherals, and often by simple
refusal to use interface circuits.
The author of these lines tried to summarize all the experience he received from similar experiments and all the information that is currently known to him. Below you will find information and diagrams on how to properly
use interface devices on SPECTRUM and their variants
tested and used for a long time on several computers like
"PENTAGON-128". Thisthe construction option does not change the software
compatibility at the level of ZX machines for application and gaming software
products of both foreign and domestic companies in 48/128K.

Standard distribution of ports in the ZX-SPECTRUM any
configuration has the following form (if we consider the bitwise
distribution):

A15 A14 A13 A12 A11 A10 A9 A8 : A7 A6 A5 A4 A3 A2 A1 A0
________________________________________________________________________________
:
X X X X X X X X : X X X X X X X X
┬ ┬ ┬ ┬ ┬ ┬ ┬ ┬ ┬
│ <--- #XXFE keyboard port │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ #XXFE
│ │ │ 0 0* 0* │ │ 0 port
1 0 │ port #1F │ │keyboards
#FFFD #BFFD KEMPSTON JOYSTIK │ │
AY-3-8910(12) │ │ 0
music coprocessor └─ X #7B,#FB 0 ─────┘ port #XXFD
│ │ │ printer port AY-3-8910(12)
0 0 * 0 * (eg ZX-LPRINT II-III) │
port #7FFD switch port #7FFD
pages RAM-DISK (128K)RAM-DISK (128K)

-2-

As can be seen from the diagram, simplified decryption of the computer system ports greatly complicates connecting a sufficient number of
external devices. These restrictions are not difficult to trace. The above diagram shows the bits that are controlled by the decoders of the vast majority of schemes (Leningrad, Moscow, Pentagon-48,128 and many others). The keyboard 'takes over' most of the addresses (exactly half - 32768), because... all even addresses
have A0=0, then this certainly connects the keyboard port. In the same way, resetting to 0 A7 selects KEMPSTON (in Leningrad, for example, everything is done much simpler; this port occupies the remaining 32768 addresses of the full Z80 addressing, i.e. all odd addresses). If desired, this
description can be continued.
Therefore, connecting any external devices should
be done carefully and when programming, specify the full address of the
port (with "1" in unused digits). In some variants of
computers, it is natural that this cannot be done without modifications.
One of the possible solutions to this problem is the use of an additional decoder. Below will be indicated and
justifiedmethods for dividing the address space of this scheme.

For decryption, it is advisable to use the lower half of the addresses
(A7-A0), because When programming Z80 machine code, accessing such ports is simpler and faster, and nothing prevents the programmer from using full commands (for example, 'OUT A, (C)') and thus expanding the address space with higher addresses. As can be seen from the circuit discussed above, the following bits can be selected for control: 7,4,3. When using m/s K555ID7, it is possible
to completely decipher all these bits; in addition, you can use
another bit A0 to enable decryption and thus not use
all even addresses. All this must be taken into account in order to ensure
software compatibility with non-modified types of computers.
Thus, all 8 possible address combinations have the form:

A7 A6 A5 A4 A3 A2 A1 A0 │Channel │ Purpose channel
───────────────────────────────
│ │
0 X X 0 0 X X 1 │ 0 │ reserve
1 X X 0 0 X X 1 │ 1 │ port KR580VV55 (II)
0 X X 1 0 X X 1 │ 2 │ reserve
1 X X 1 0 X X 1 │ 3 │ timer KR580VI53
0 X X 0 1 X X 1 │ 4 │ reserve
1 X X 01 X X 1 │ 5 │ port KR580VV51
0 X X 1 1 X X 1 │ 6 * │ port KR580VV55 (I), standard
1 X X 1 1 X X 1 │ 7 * │ port AY-3-89XX and for long-term use
│ │ shego extensions
───────────────────────────── ──┴──────┴─────────── ──────────────────
* - Devices that cannot be disconnected from the ZX buffer system bus are marked.

-3-

Decoder circuit:

K555ID7
┌───┬─────┬───┐
1 │ │ DC │ │15
A7' ────────┤A0 │ │ 0 ├───────> CHANNEL 0 - reserve
2 │ │ │ │14
A4' ────────┤A1 │ │ 1 ├───────> CHANNEL 1 - KR580VV55(II)
3 │ │ │ │13
A3' ────────┤A2 │ │ 2 ├───────> CHANNEL 2 - reserve
│ │ │ │12
│ │ │ 3 ├───────> CHANNEL 3 - KR580VI53
│ │ │ │11
├───┤ │ 4 ├───────> CHANNEL 4 - reserve
──── 4 │ ─ │ │ │10
* OIRQ'────────┤E1 │ │ 5 ├───────> CHANNEL 5 - KR580BB51
5 │ ─ │ │ │9
+5V ─▓▓▓─▄────────┤E2 │ │ 6 ├────> CHANNEL 6* >───┐
10K │ 6 │ │ │ │7 │ ┌───┐
│ A0'────┤E3 ││ 7 ├──┐ CHANNEL 7* └────┤1 │ BB55
│ │ │ │ │ │ │ ├────>
ON │ OFF └───┴─────┴───┘ │ ┌───┐ A2'────┤ │
Interface/ S1 └──┤1 │ └───┘
│ │ ├────> #XXFD K555LL1
│ A1'────────────────────┤ │ (AY-3-89XX)
▀▀▀ └───┘
Switch S1 is designed to disable the decoder (and
devices connected to it) for debugging purposes or if it is necessary to temporarily restore the configuration of your ZX to its “original form”.
The OIRQ signal is a signal usually received from the TR-DOS controller
OUT_IORQ - an active request to the input/output ports when DOS IS NOT
ACTIVE! This signal, in its absence, can be easily obtained by adding the OR signals IORQ (Z80) and DOSEN (from the K555TM2 trigger of the TR-DOS/SOS control ROM).

An important issue for the user is the use of buffering of the computer system bus. Although few people go for this,
wanting to quickly “attach” a limited number of peripherals to the Z80 and
believing that he will not go further than this. Although on 48K machines due to their
low load on the processor (or the use of CPUs with increased load
capacity of companiesSHARP, GOLD STAR, NEC, etc.) this option sometimes
passes, only occasionally tormenting owners at the most inopportune moment
with various crashes and 'freezes', but with an increase in the desired peripheral
or the transition to 128K ZX, normal computer operation is violated.
Therefore, everyone who is ready to seriously use their SPECCY, without constantly thinking
about the fact that in an hour or two the results of its work may suddenly disappear, is suggested to make a system buffer.
It is recommended to carry it out on a separate (in the form of a breadboard) board
together with unchangeable devices discussed in this text, and transfer from the main board to it all the signals that are needed or may be needed later. This will allow you to remove a full-fledged buffered system bus from the computer and will protect the computer itself from various 'accidents' such as a "tragic
hit of 12V on the data bus of an external device", which will certainly
disable the processor, EPROM, RAM and a couple more chips.

-4-

Data bus buffers and CPU addresses Z80:

K555AP6
┌───┬─────┬───┐
2 │ D1 ──────┤A1 ││B1 ├───────> D1'
S 4 │ │ │ │16
P D2 ──────┤A2 │ │B2 ├───────> D2'
E 5 │ │ │ │15
C D3 ──────┤A3 │ │B3 ├───────> D3' Выход буфеpа
T 6 │ │ │ │14
R D4 ──────┤A4 │ │B4 ├───────> D4' шины данных
U 7 │ │ │ │13
M D5 ──────┤A5 │ │B5 ├───────> D5'
8 │ │ │ │12
D6 ──────┤A6 │ │B6 ├───────> D6'
9 │ │ │ │11
D7 ──────┤A7 │ │B7 ├───────> D7'
│ │ │ │
├───┤ ├───┤
── 1 │ │ │ │20
RD ──────┤A/B│ │Ucc├────> +5V В данных включениях м/сх
9 │ ─ │ │ │10 возможно пpименение и дpугих
┌────┤EO │ │GND├────┐ типов буфеpов пpедназначен-
│ │ │ │ │ │ ных для pаботы в шинных фоp-
│ └───┴─────┴───┘ ▀▀▀▀ миpователях : К555(1533)АП4,
│ АП5,АП6,АП7,КР580ВА86.
└───────────────────────────┐ В буфеpе ШД - КР580ВА86 (из-
4 ┌───┐ │ за двунапpавленности) , АП6.
A0'────────┤ & │ 6 4 ┌───┐ │
5 │ o────────┤1 │6 │
A2'────────┤ │ 5 │├────┘
──── └───┘ ┌─────┤ │
* OIRQ' ──────────────┘ └───┘

К555ЛА3 К555ЛЛ1

К555АП6 К555АП6
┌───┬─────┬───┐ ┌───┬─────┬───┐
2 │ │ BD │ │18 2 │ │ BD │ │18
A0 ─────┤A0 │ │B0 ├────> A0' A8 ─────┤A0 │ │B0 ├────> A8'
│ │ │ │ │ │ │ │
.. .... │.. │ │.. │ ... .. .. .... │.. │ │.. │ ... ..
9 │ │ │ │11 9 │ │ │ │11
A7 ─────┤A7 │ │B2 ├────> A7' A15 ─────┤A7 │ │B2 ├────> A15'
│ │ │ │ │ │ │ │
├───┤ ├───┤ ├───┤ ├───┤
1 │ │ │ │20 1 │ │ │ │20
+5V ─────┤A/B│ │Ucc├───> +5V +5V ─────┤A/B│ │Ucc├────> +5V
9 │ ─ │ │ │10 9 │ ─ │ │ │10
┌───┤EO │ │GND├───┐ ┌───┤EO │ │GND├───┐
│ │ │ │ │ │ │ │ │ │ │ │
▀▀▀ └───┴─────┴───┘ ▀▀▀ ▀▀▀ └───┴─────┴───┘ ▀▀▀

-5-

Знаком (') отмечены выходные сигналы котоpые в дальнейшем должны
использоваться для подключения пеpифеpии.

In a similar way, it is advisable to buffer the control signals
Z80:

K555AP6
┌───┬─────┬───┐
── 2 │ │ BD │ │18 ──
Z RD ────────┤A0 │ │B0 ├───────> RD'
X ── 3 │ │ │ │17 ──
WR ────────┤A1 │ │B1 ├───────> WR'
S ─── 4 │ │ │ │16 ───
P OIRQ* ────────┤A2 │ │B2 ├───────> OIRQ*'
E 5 │ │ │ │15
C CLK 3.5 ───────┤A3 │ │B3 ├───────> 3.5' Mhz
T 6 │ │ │ │14
R CLK 2.0 ───────┤A4 │ │B4 ├───────> 2.0' Mhz
U 7 │ │ │ │13
M CLK 1.75 ──────┤A5 │ │B5 ├───────> 1.75' Mhz
───── 8 │ │ │ │12 ─────
RESET ───────┤A6 │ │B6 ├───────> RESET'
9 │ │ │ │11
reserve ───────┤A7 │ │B7 ├───────>
│ │ │ │
├───┤ ├───┤
1 │ │ │ │20
+5V ────────┤A/B│ │Ucc├────> +5V
9 │ ─ │ │ │10
┌────┤EO │ │GND├────┐
│ │ │ │ │ │
▀▀▀ └───┴─────┴───┘ ▀▀▀

It is advisable to install the data bus buffer on the socket, because during
experiments 'victim'' often he becomes the one. The SD buffer is automatically disconnected from the bus when the computer accesses (read/write) ports #7B, #FB and #FE. In 128K computers, port #XXFD
is still not controlled by this circuit, however, when accessing
the registers of the music coprocessor (read/write), everything happens
correctly, because AY connects via buffer; when accessing
RAM-DISK (#7FFD), only writing is done to this port and, in principle, it does not matter that the buffer passes data through itself. In the mode of
maskable processor interrupts ( IM0,IM2 ), even if the addresses A0=1, A2=1 match, the IORQ signal is activated, which removes the SD buffer from the Z-state, but the RD signal is inactive in the Z80 interrupt confirmation cycle switches the direction of the buffer in such a way that it is connected to the CPU bus by inputs. Thus, the buffer does not change
the state of the bus and in the absence of an active device on it in the interrupt confirmation cycle, the vector read by the processor does not
change and in the ZX-SPECTRUM without INTERFACE-1 connected is equal to #FF.
Because Such a device is more than a rarity in our country; it is not recommended to change the interrupt vector in hardware (except for devices specially designed for this mode) because this will make it inoperableprograms using the IM0,IM2 mode.

-6-

The use of a programmable parallel adapter
BIS KR580BB55(A) in the computer significantly expands the further operation of the machine
and allows the user not to worry about connecting 'not
very fast' devices in the future working in parallel code
(printers, ADC, DAC, microcircuit diagnostic devices, programmer, etc.). Software support via the port simplifies the interface and makes it more compact. If there is still a need to use
several similar ports simultaneously (for example, in an advanced
ROM programmer), it is advisable to connect via the system bus, because the number of connecting wires is reduced, and use
internal signals CHANNEL-0,..,5 for CS of these devices.
The main port of KR580BB55A is connected to CHANNEL-6 as follows:

┌───┬─────┬───┐
│ │ PPI │ │
Data bus │D0 │ │A0 │
data < ███████ >│.. │ │.. │< ███████ > channel A
D0'-D7' │D7 │ │A7 │
│ │ │ │
│ │ │ │
6 ├───┤ │ │
CHANN.-6 ─────────┤CS │ │B0 │
─ 36│ ─ │ │.. │< ███████ > channelB
WR' ─────────┤WR │ │B7 │
─ 5 │ ─ │ │ │
RD' │ │ │
├───┤ │ │
9 │ │ │C0 │
A5 ─────────┤A0 │ │.. │< ███████ > channel C
8 │ │ │C7 │
A6 ─────────┤A1 │ │ │
│ │ │ │
───── ┌──┐ 35├───┤ │ │
RESET' ──┤1 o──▄──┤R │ │ │
└──┘ │ │ │ │ │
K555LH1 │
└───> RESET'

The main port is connected to the standard addresses for this device:

#1F - channel A
#3F - channel B
#5F - channel C
#7F - control word register

-7-

In addition, because after the initial reset, BB55 is set to
mode "0" and channel A is programmed for input (after receiving the
RESET signal), that is, it is possible to use this channel for KEMPSTON
JOYSTIK (standard address - #1F). The device is connected
to the 5 least significant bits of port A, the most significant bits must be grounded,
since. Most programs use this feature to determine that the
KEMPSTON interface is connected. True, when accessing the standard
interface of the ZX-LPRINT II-III printer (read/write #7B) port
simultaneouslygets out and can disrupt its work schedule. Although such
operation of devices in the presence of a SD buffer does not lead to a mutual
conflict on the bus, it is advisable to disable the decoder during printing
(OFF Interface) or provide additional
control of address A2 for the CS port (control this address by OR, see above).
However, this issue can not be considered if the ZX-LPRINT is inactive
(the ENPR input is not grounded) or in the program after printing is completed, the port
BB55 is reconfigured again, at least completing the decryption
in this way (the issue with AY-3-89XX), this problem
will cease to exist.

-8-

If there is a music coprocessor AY-3-8910(12), the decoder
must also be supplemented with a circuit for monitoring high-order addresses:

AY-3-8912
┌────┬─────┬────┐17
───── 16 │─── │ SSG │ A& ├───┐
RESET' ────────┤RES │ │ │19 █───> +5V
│ │ │BC2 ├───┘
├────┤ ├────┤
28 │ │ │ │14
D0' ────────┤D0 │ │IO0 ├───────>
27 │ │ │ │13
D1' ────────┤D1 │ │IO1 ├───────> PARALLEL PORT
26 │ │ │ │12
D2' ────────┤D2 │ │IO2 ├───────>
25 │ │ │ │11 ▄▄▄ ▄▄▄
D3' ────────┤D3 │ │IO3 ├──────> │ │
24 │ │ │ │10 ▓ 10k ▓ 10k
D4' ────────┤D4 │ │IO4 ├──────> ▓ ▓
23 │ │ │ │9 │ 5.0 + │
D5' ────────┤D5 │ │IO5 ├──────> █────█───────┤├──┼─────> L
22 │ │ │ │8 │ │ ┌─────█──┤├─> R
D6' ────────┤D6 │ │IO6 ├──────> │ │ │ │ 5.0 +
21 │ │ │ │7 ▓ ▓ ▓ ▓
D7' ────────┤D7 │ │IO7 ├──────> ▓10k ▓ 20k ▓ 20k ▓ 10k S
├────┤ ├────┤5 │ │ │ │ O
15 │ │ │ A ├──────────█ │ │ │ U
CLK 1.75' ─────┤CLK │ │ │4 │ │ │ │ N
│ │ │ B ├──────────┼────█─────█ │ D
├────┤ │ │1 └────┐ │ │
18 │ │ │ C ├───────────────┼─────┼─────█
┌─────┤BDIR│ ├────┤3 │ │ │
│ 20 │ │ │Ucc ├───> +5V │ │ │
│ ┌───┤BC1 │ │ │6 ▓ ▓ ▓
│ │ │ │ │GND ├───┐ ▓ 10k ▓ 10k ▓ 10k
│ │ └────┴─────┴────┘ ▀▀▀ │ │ │ M
│ └────────────────────────────────┐ └─────█─────█──┤├─> O
└────────────────────────────────┐ │ │ + N
── ЛА3 ЛЕ1 ┌───┐ │ │ ▓ 5.0 O
WR' ──────────────────────────────┤1 │ │ │ 10k ▓
┌───┐ ┌───┐ │ о──┘ │ │
A13' ────┤& │ ┌─────┤1 │ ┌──┤ │ │ ▀▀▀
│ о────┘ │ ├───▌ └───┘ │
A15' ────┤ │ ┌─────┤ │ │ ┌───┐ │
── └───┘ │ └───┘ └──┤1 │ │
#FD ─────────────┘ К555ЛЛ1 │ o────┘
┌───┐ ┌──┤ │
A14' ───────────────────┤1 │ │ └───┘
── ┌───┐ │ o───┘ К555ЛЕ1
RD' ────┤& │ ┌─────┤ │
│ o────┘ └───┘
+5V ────┤ │ К555ЛЕ1
└───┘
К555ЛА3

-9-

Интеpфейс ноpмально pаботает пpи обpащениях чтение/запись к
любым поpтам ввода вывода, успевая пеpеключать напpавление и
Z-состояние (это связано с наличием дополнительного цикла ожидания у
Z80 пpи pаботе с внешними устpойствами), однако не следует
модифициpовать схему с цельлью подключения чеpез буфеp ШД 'быстpые'
устpойстваtype m/sx PROM or other devices with which the processor
works through memory access commands. At a given clock frequency of the Z80, the buffer does not have time to enter the Z-state and partially blocking the computer data bus disrupts its normal operation.
The interface allows connecting devices with a cable up to 1 m long
without degrading the characteristics.

(C) UA3PRQ for HAMs
Uzlovaya, 28 June 1993.

> end ZX_EXTEN.TXT

VG> All the best. Sincerely, Vitaliy.
VG> //The dollar exchange rate in Lisichansk is $5.47 for 1 hryvnia.
That’s it, I’m going to exchange cars ;)

Always yours Combin8or/PH7

VG> AP-6 for buffering the address bus.
Man! Don't suffer like that! The address bus is unidirectional and using AP6 to buffer it is like hammering nails with a calculator.
Install a couple of IP12s and everything is fine. If you need pinouts, then I’ll throw in some soap.

*Write letters. Alex was here.*

*[Metallica]* *[ScorpionS FidoFanClub]* *[Manowar]* *[Life Is Love]*

Better than AP5, IR33. You just solder it to the processor outputs, and then the buffer outputs into the circuit. Of course, you need 2 buffers.

Bye, Yuri.

[I ZX] [Chemists] [For full address] [Ski poles]

/_500:322/33@ZXNet_/ /_dang...@bigfoot.com_/ /_dang...@mail.ru_/
/_2:462/93.33@FidoNet_/

... Dig a hole for yourself and make the work of others easier.