Answer about AY-3-8910 [1/2]
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about the Question about AY-3-8910 and I decided to intervene.
├┤i Yan & All !
[...]
YZ> SUBJECT. After the tragic death of one of the Spectrums, I have
Cut it out and nail it to the wall.
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Music processors AY-3-8912/AY-3-8910 from General
Instruments (GI) and YM2149F from YAMAHA (analogue AY-3-8910).
Characteristics.
1. Software control of the generator.
2. Three program-independent analog outputs.
3. Two (one for AY-3-8912) 8-bit universal input/
output ports.
Description:
Programmable Sound Generator (PSG) allows you to reproduce
a wide range of wide-range sound effects.
It is compatible with 16-bit microprocessor controllers such as the CP1600/1610 Communications Processor and 8-bit programmable
interface controller PIC1650.
Each of the three analog channels of the PGZ reproduces the sound picture by decoding a binary code on a logarithmic scale.
All control signals of the PGZ are digital and are generated directly in the microprocessor, which makes it possible to do without
changes in circuitry.
To communicate the PGZ with the microprocessor in The AY-3-8910 has two universal 8-bit I/O ports, andits case has 40 pins. The AY-3-8912 has one port and 28 pins.
Pin assignments of the chips.
DA7-DA0 is a tri-state data/address bus.
Pins 30-37 in the AY-3-8910.
Pins 21-28 in the AY-3-8912.
This is an 8-bit bidirectional bus designed for forwarding
addresses and data by the processor and the PGZ itself. In data mode, DA7-DA0
corresponds to bits B7-B0 of the generator register area. In address mode, DA3-DA0 occupy the number of the selectable register (0-17),
and DA7-DA4 in combination with address inputs A8 and /A9 form the high
part of the address.
A8 (input) - pin 25 (17) AY-3-8910 (AY-3-8912).
/A9 (input) - pin 24 AY-3-8910, not supported in AY-3-8912.
Address buses A8 and /A9.
The PGZ memory area consists of 16 8-bit words included in the total 1024-word memory of the @KOM= system. It is precisely with the help of these
address buses that the addressing of the PGZ memory is expanded from 256
(DA7-DA0) 1 to 1024 words.
If the memory size of the real "PGZ-computer" system does not allow
the use of these buses, then they are not connected during installation of the system
because each of them is equipped with an internal supporting (for A8) or quenching (for /A9) resistor. If these buses are not used in “noisy” environments, it is necessary that they be connected to a common bus
“+5V” and"EARTH", respectively.
/RESET (input) - pin 23 of AY-3-8910, pin 16 of AY-3-8912.
Used to initialize the PGZ and set its blocks to their initial state by applying a logical zero to the output. In this case, the entire
register area of the PGZ memory is reset to zero. The output is equipped
with an internal backup resistor.
┌──────┬─┬──────┐
GROUND ─┤ 1 └─┘ 40├─ +5V
not used. ─┤ 2 39├─ TEST 1
analog. channel B ─┤ 3 AY-3-8910 38├─ analog. channel C
analogue channel A ─┤ 4 YM2149F 37├─ DA0
not used. ─┤ 5 36├─ DA1
IOB7 ─┤ 6 35├─ DA2
IOB6 ─┤ 7 34├─ DA3
IOB5 ─┤ 8 33├─ DA4
IOB4 ─┤ 9 32├─ DA5
IOB3 ─┤10 31├─ DA6
IOB2 ─┤11 30├─ DA7
IOB1 ─┤12 29├─ BC1
IOB0 ─┤13 28├─ BC2
IOA7 ─┤14 27├─ BDIR
IOA6 ─┤15 26├─ TEST 2
IOA5 ─┤16 25├─ A8
IOA4 ─┤17 24├─ /A9
IOA3 ─┤18 23├─ /RESET
IOA2 ─┤19 22├─ CLOCK
IOA1 ─┤20 21├─ IOA0
└───────────────┘
CLOCK (input) pin 22 AY-3-8910, pin 15 AY-3-8912.
Used to supply clockfrequency that sets the timing parameters of the noise, tone and envelope generators.
Input TTL-compatible.
BDIR, BC2, BC1 (inputs) pins 27, 28, 29 AY-3-8910,
pins 18, 19, 20 AY-3-8912.
Control buses - BUS DIRECTION, BUS CONTROL 1,2.
Used to control all external and internal bus
operations in the PGZ. The signals for these buses are generated directly by the communication processor type CP1600.
When using another processor, these signals must be generated by similar bus signals of the processor being used or
simulated on the input/output buses of the main microprocessor
of the system. Decoding of control signals is given in table.
┌─────┬─────┬─────┬──────────────┐
│BDIR │ BC2 │ BC1 │Function CP1600│
├─────┼─────┼─ ────┼──────────────┤
│ 0 │ 0 │ 0 │ NACT 0 │ 0 │ 1 │ ADAR 0 │ 1 │ 0 │ IAB 0 │ 1 │ 1 │ DTB 1 │ 0 │ 0 │ BAR 1 │ 0 │ 1 │ DW 1 │ 1 │ 0 │ DWS 1│ 1 │ 1 │ INTAK │
└─────┴─────┴─────┴──────────────┘
To use all the capabilities of the generator To create sound pictures, it is enough to have only four combinations of signals
BDIR, BC1, BC2. This is achieved by connecting BC2 to the power bus +5V.
┌─────┬─────┬─────┬──────────────┐
│BDIR │ BC2 │ BC1 │Function CP1600│
├─────┼─────┼─────┼──────────────┤ │
│ 0 │ 1 │ 0 │not active │ from │──>BDIR
├─────┼─────┼─────┼──────────────┤ processor <─────BC2(+5V)
│ 0 │ 1 │ 1 │reading from PGZ │ to PGZ │──>BC1
├─────┼─────┼─────┼──────────────┤ │
│ 1 │ 1 │ 0 │record in PGZ 1 │ 1 │ 1 │fixed addresses│
└─────┴─────┴─────┴──────────────┘
Analog channels A, B, C (outputs) pins 4, 3, 38 AY-3-8910
pins 5, 4, 1 AY-3-8912
Used to generate a composite audio signal with
double amplitude up to one volt. They are the output
signals of the corresponding digital-to-analog converters (DACs).
IOA7-IOA0 (input/output) pins 14-21 AY-3-8910,
pins 7-14 AY-3-8912.
IOB7-IOB0 (input/output) pins 6-13 AY-3-8910
in AY-3-8912 are not supported.
A7-A0 I/O,B7-B0.
They are parallel input/output ports. Used for
data exchange with external devices connected to
IOA or IOB contacts via the generator-processor bus. All pins are equipped with
internal backup resistors, so the input mode will
read a normal high level.
┌──────┬─┬──────┐
analog. channel C ─┤ 1 └─┘ 28├─ DA0
TEST 1 ─┤ 2 27├─ DA1
+5V ─┤ 3 AY-3-8912 26├─ DA2
analog. channel B ─┤ 4 25├─ DA3
analog. channel A ─┤ 5 24├─ DA4
GROUND ─┤ 6 23├─ DA5
IOA7 ─┤ 7 22├─ DA6
IOA6 ─┤ 8 21├─ DA7
IOA5 ─┤ 9 20├─ BC1
IOA4 ─┤10 19├─ BC2
IOA3 ─┤11 18├─ BDIR
IOA2 ─┤12 17├─ A8
IOA1 ─┤13 16├─ /RESET
IOA0 ─┤14 15├─ CLOCK
└───────────────┘
TEST 1 pin 39 AY-3-8910, pin 2 AY-3-8912.
TEST 2 pin 26 AY-3-8910, not supported in AY-3-8912.
Intended for testing the generator and therefore are not used in real
circuits. The peculiarity is that these conclusions
must always be free.
Block diagram of the generator connection.
┌─────────┐ ┌─────────┐
│ │ │ PGZ │ ┌─────┐
│ │ tire │ │ │ │
│micropro-│<──────────>│ │>───────────>│ │
│cessor│ adr./data. │ │ address input │ P │
┌──>│system │<──────────>│ │>───────────>│ A │
│ │ │ tire │ │ │ M │
│ │ T │
│ └─────────┘ │ │ data entry │ b │
│ │ │>───────────>│ │
│ │ │ │ │
│ │ │ └─────┘
│ │ │
│ │ │ ┌─────┐
│ ┌─────────┐ │ A│────────────>│ │
│ │clocked │ │ B│────────────>│ UHF │
└───│generator│───────────>│ C│────────────>│ │
│systems │ │ │ └─────┘
└─────────┘ └─────────┘
Architecture.
The interaction between the AY-3-8910/8912 and the processor is based on
the principle of memory snapshot input/output. A set of commands intended for PGZ is written insixteen-register memory area.
The microprocessor can read the contents of any of the 16 registers with or without
changing their state. All registers are programmed
at one time and the PGZ begins to generate sound, freeing the processor
to perform other operations.
Register area.
The sixteen eight-bit PGZ registers are considered by the processor as a memory block located behind the maximum memory address -
consisting of 1024 bytes. The ten address bits are decoded
as follows: way:
┌───┬───┬───┬───┬── ─┬───┬───┬───┬───┬───┐
│/A9│ A8│DA7│DA6│DA5│DA4│DA3│DA2│DA1│DA0│
├── ─┼───┼───┼───┼───┼─── ┼───┼───┼───┼───┤
│ 0 │ 1 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │
└───┴───┴───┴───┴─ ──┴───┴───┴───┴───┴───┘< p>┌───┬───┬───┬───┬───┬─ ──┬───┬───┬───┬───┐
│ 0 │ 1 │ 0 │ 0 │ 0 │ 0 │ 1 │ 1 │ 1 │ 1 │
└───┴───┴───┴───┴─── ┴───┼───┴───┴───┴───┘
high part │ low part
(chip selector) │ (register number)
Four bits of the low part of the address set the number of one of 16 registers, and 6 bits of the high part of the address represent a selector and control three states of bidirectional buffers (if
an error in the high part of the address of the buffer is transferred to the high state resistance). Bits DA7-DA4 of the high part of the address can
perform the role of a mask containingfour-digit code, available
modifications. If their use is not intended, then they
must be in the "0000" state.
If there are no errors in the high part of the address, then the address of the control register is placed in the decoder block address fixing register.
The register address is fixed and operations with the selected register are carried out until the generator receives a signal about the address change.
Data coming from the address/decoder fix register addresses
and the state of bidirectional buffers specify the function of the generator:
inactive, address fixation, reading or writing data. These
states are formed by the control signal decoding block.
Sound generator blocks.
The main blocks are:
- tone generators that form the main
tone frequency for each channel;
- a noise generator that generates for each channel
a sequence of pulses of pseudo-random duration;
- mixers that combine the output signals of tone generators and noise generator for each of the channels;
- amplitude regulator - produces control signals for
digital-to-analog converter (DAC), setting the sample amplitude of the signal produced by the generator at a given time;
- envelope generator - producesenvelope sample used
for amplitude modulation of channel output signals;
- DAC of each channel - generates an output audio signal with 16
amplitude levels set by the amplitude control.
Input/output ports.
The PGZ contains two input/output ports (A and B). The processor
through them exchanges data with the PGZ without causing
the generation of sounds. Port B is not supported in the AY-3-8912.
PGZ operation.
Sixteen registers are divided into groups that specify
the sequence of generator functions and their parameters. The
table below shows the generator blocks and their corresponding control units. registers.
Table.
┌───────────┬───────── ──┬──────────────────── ─────────────┐
│blocks generator │control│ functions of registers │
│rator │registers │ │
├───────────┼───────────┼───────── ────────────────────────┤
│tone │ R0-R5 │period programming │
│oscillators │ │pitch tone │
├───────────┼───────────┼─────────
│generator │ R6 │programming the noise period │
│noise │ ││
├───────────┼───────────┼───────── ────────────────────────┤
│mixers │ R7 │programming the order of │
│ │ │supplying tone and/or noise to one of│
│ │ │selected channels A, B or C │
├───────────┼───────────┼───────── ────────────────────────┤
│regulator │ R10-R12 │programming the order of change- │
│amplitude │ │the amplitude of the output signal │
├───────────┼───────────┼─────────
│generator │ R13-R15 │programming the period and shape of the │
│envelope │ │we are the envelope of the output signal │
└───────────┴─── ────────┴───────────── ────────────────────┘
==================== cut line ====================
To be continued...
Reply to: Kirill_Fro...@zxnet.spb.ru
KF> Cut it out and nail it to the wall.
Wow! What a great description =)
Thank you.
KF> A8 (input) - pin 25 (17) AY-3-8910 (AY-3-8912).
KF> /A9 (input) - pin 24 AY-3-8910, not supported in AY-3-8912.
KF> Address buses A8 and /A9.
KF> The PGZ memory area consists of 16 8-bit words,
KF> included in the total 1024-word memory of the @KOM= system. It is with
KF> with the help of these
KF> address buses that the PGZ
KF> memory addressing is expanded from 256
KF> (DA7-DA0) 1 to 1024 words.
What kind of memory is there? Well, the one that is addressed by these A8 and /A9
?
KF> To use all the capabilities of the
KF> generator for creating sound patterns, it is enough to have only four combinations of
KF> signals
KF> BDIR, BC1, BC2. This is achieved by connecting BC2 to
KF> power bus -
KF> +5V.
Why then BC2? The bourgeoisie wouldn't make this BC2 ;)
See you. Jan Zagorskikh.