description of HDD ports [1/3]

ZXNet echo conference «real.speccy»

From Valerij Kozhevnikov (500:95/162. To All 7 April 1998

Hello, Roman!

I give a full description with minor abbreviations. It's not completely typed here, there's also a list of commands, the format of the passport,
the purpose of the connector contacts, etc., etc.
I'll probably post the circuit diagram tomorrow, I just lost the list of micros, summaries, etc. somewhere.
If I made a mistake somewhere, ask. Almost certainly something
forgot or lost.

AM - address marker
KCC - control cyclic code
HOST - control computer
ECC - error detection code
CRC - KCC

Structurally, the controller contains two devices: a controller
512k RAM and a HDD controller. On the same board there is also an XT keyboard controller, but it is completely independent and is not described here.

#FCAF (out) - control of the controller configuration.

bit 7,1
- high-order bits that form the number of the video page displayed in
640*200 mode.

bit 0
- (=1) connection of the RAM configuration port 512k.

bit 4
- (=1) blocking the reset of the controller configuration port.

bit 5
- (=1) blocking writing and reading of all controller ports.

bit 6
- (=1) hardware reset of the HDD.

#FDAF (out) - RAM configuration port.
I won’t give it in full, but in fact you can have 4 independent ones 128 cars. That is, in any of the three lower segments, one of the four pages can be substituted, and from the address
#C000 - any of the 32 available ones.

┌─────────┬─────────────┐
│ Segment │ Pages │
├─────────┼─────────────┤
│ #0000 │ 0,8,16,24 │
│ │ │
│ #4000 │ 5,13,21,29 │
│ │ │
│ #8000 │ 2,10,18,26 │
│ │ │
│ #C000 │ any │
└─────────┴─────────────┘

Next, all about the screw.
I’ll say right away: do not abuse software/hardware resets
worth it. The propeller parks the heads and the engine performs stop/acceleration. This will not add to his life.
I completely ruled out a hardware reset: I tore off the 1st contact from
the cable, and that’s it OK.

┌───────┬───────────────────────
│ │ IN │ OUT │
╞═══════╪════════════════════════
│ #FDAF │ Data register D8-D15 │ not used │
│ #FFAF │ not used │ Data register D8-D15 │
│ #FEAF │ Data register D0-D7 │ Data register D0-D7 │
│ #F6AF │ Error register │ Precompensation register │
│ #EEAF │ Sector Counter Register │ Sector Counter Register │
│ #E6AF │ Sector Number Register │ Sector Number Register │
│ #DEAF │ Cylinder Number Register │ Cylinder Number Register │
│ │ (low) │ (low) │
│#D6AF │ Cylinder Number Register │ Cylinder Number Register │
│ │ (high) │ (high) │
│ #CEAF │ Accumulator/Head Register│ Accumulator/Head Register │
│ #C6AF │ Status Register │ Command Register │
├───────┼────────────────────────
│ #CAAF │ Alternate register │ Control of storage │
│ │ state │ power supply │
│ #C2AF │ Drive address register │ not used │
└───────┴───────────────────────

Data registers #FDAF, #FEAF, #FFAF are used when performing sector read/write operations in software I/O mode. The #FEAF register is not accessible until a read or write operation begins. Data transmission is carried out in 16-bit words. When reading from the #FDAF port, bits D8-D15 of the HDD data register are read. To read them correctly
it is first necessary to read bits D0-D7 (port #FEAF)
of the HDD data register.

* This method of data transfer is adopted due to the fact that the
word size for HDD IDE is 16 bits and the bus size is 8 bits. Therefore, one word of data is transmitted/received by two IN/OUT commands.
However, to speed up I/O operations, the port addresses are arranged like thisso that it is possible to use the INI-
/OUTI commands.

For example, reading one word:

LD HL,BUFFER
LD BC,#FEAF
INI
INI

or writing:

LD HL,BUFFER
LD BC,#00AF
OUTI
OUTI

* Address #00AF is taken because what the OUTI command does is DEC B
before forwarding to the port.

Jason.