HDD & SPECCY

I've been thinking about connecting a screw to my computer for a long time, but I just can't decide
what scheme to do it with.

If anyone already has a subj, please write what scheme, through what
ports, maybe a diagram with soap.

And one more thing... if anyone has assembled a HDD controller from ZF#8, please write your reviews
on the operation of this scheme (conflicts with other peripherals, etc.). d.)

Thank you in advance!

Sincerely, Sergey Karachentsev.

31 Aug 1999 you wrote here:

SK> I’ve been thinking about connecting a screw to my computer for a long time, but I just can’t
SK> decide which scheme to do it with.

What, you have a very wide choice?!

SK> If anyone already has a subj, please write what scheme, through which
SK> ports, maybe a scheme soap.

I saw only 2 circuits. Nemov's (from ZF#8) and ZXNext's.
Software I saw only for one - Nemov's.
So I had little choice - Nemov's.
Although, apparently, I may soon see software for ZXNext's, then
I'll remake it for it.

SK> And also... if whoever assembled the HDD controller from ZF#8, please write your
SK> reviews on the operation of this circuit (conflicts with other peripherals, etc.)

Caution, in the circuit from ZF#8 there is a typo - the 11th leg of D6.2 should be supplied with A3
instead of A5. Otherwise, everything is fine, it works.

All the best.
Sincerely, Roman.

RM> I saw only 2 schemes. Nemov's (from ZF#8) and ZXNext's.
RM> I saw software for only one - Nemov's.
RM> Therefore, my choice was small - Nemov's.
RM> Although, apparently, I may soon see software for
RM> ZXNext's, then
RM> I will redo it myself for it.

I also wanted to build Nemovskaya, but recently I began to be tormented by the question: isn't such a weak decryption of the ports of this scheme dangerous for the information on the screw
?
For me, the safety of information is the main priority.
Moreover, I decided to make the ports of all peripherals available in both SOS and
DOS (with the exception of VG93 and VV55).
I think it should be done. 16-bit ports: the low byte is the port number of the screw controller, the high byte is for selecting the internal registers of the HDD. At the same time
the circuit should not be more complicated than Nemov's.
Strictly, I only need the port number and the optimal arrangement of the control bits.
On the same board with the controller I am going to place the circuit
CMOS clock using GLUK without using the #EFF7 port.

If there is information on ZXNext's screw connection circuit
please convey.

Sincerely, Sergey Karachentsev.

÷دش ة ذpةغإج ـشدش ؤدجادضؤءخخظت ؤإخط!
َبإحء Sprinter-د×سثداد HDD!

üشد ذإp×ءر ×إpسةر, ذدـشدحص, ×دعحدضخظ خإشدقخدسشة.
يةخةحءجطخءر ًىي, × ثدشدpصہ حدضخد عءغةشط سبإحص صذpء×جإخةر, سشدةش خء ؤءخخظت
حدحإخش $2.24. ÷ ؤد×إسدث ث HDD × ـشص ًىي حدضخد عءغةشط إفإ قشد-شد. Hءذpةحإp,
سبإحص صذpء×جإخةر ؤجر CMOS قءسد×, COVOX-ء ةجة قإاد جةآد إفإ.
هسشإسش×إخخد, جداةثص حدضخد سدآpءشط ة خء pءسسظذصبإ. َجإؤصإش عءحإشةشط, قشد ؤجر
Sprinter-د×سثداد ثدخشpدججإpء HDD إسشط ة ذpدةاpظ×ءشإجط CD-ROM ة ؤpءت×إpء ؤجر
pءآدشظ س ئءتجد×دت سةسشإحدت CDFS
Hإش خةثءثةب ذpدآجإح س آدجطغةحة ×ةخقإسشإpءحة ة ذدؤثجہقإخةإح MASTER/SLAVE
لؤpإسء ثدخشpدججإpء ذدؤدآpءخظ شءث, قشد آظ خإ ثدخئجةثشد×ءشط س ءؤpإسءحة
#xF,#xE,#x7,#x6. ل شءث ضإ ؤجر صؤدآسش×ء ذpداpءححةpد×ءخةر سقةشظ×ءخةر/عءذةسة
سإثشدpد× ثدحءخؤءحة OUTI/INI

=== Cut ===
¥                                        ¸                      ¨
، ، Designed by Ivan Mak ،
، HDD ثدخشزدججإز ثدحذطہشإزء Sprinter. ، FIDO: 2:5030/529.24 ،
، ، (C) 1999 Peters-Plus ،
±                                        »                      µ
، َبإحء ذزإؤخءعخءقإخء ؤجر ×دعحدضخداد ذد×شدزإخةر ة صسشءخد×ثة خء ،
، ثدحذطہشإزظ شةذء ZX-Spectrum, ء شءث ضإ ؤجر ذدخةحءخةر جداةثة ،
، زءآدشظ HDD ثدحذطہشإزء Sprinter ،
±                                                               µ
، "âصئإزظ" ،
، ëز1533لً6 ،
، ‚€€ˆ€€€€ˆ€€ƒ ،
، D0€€€€€€‡D0پ RG پQ0†€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€ˆ€WD0 ،
، D1€€€€€€‡D1پ پQ1†€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€ˆ€€WD1 ،
، D2€€€€€€‡D2پ پQ2†€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€ˆ€€€WD2 ،
، D3€€€€€€‡D3پ پQ3†€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€ˆ€€€€WD3 ،
، D4€€€€€€‡D4پ پQ4†€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€ˆ€€€€€WD4 ،
، D5€€€€€€‡D5پ پQ5†€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€ˆ€€€€€€WD5 ،
، D6€€€€€€‡D6پ پQ6†€€€€€€€€€€€€€€€€€€€€€€€€€€€€€ˆ€€€€€€€WD6 ،
، D7€€€€€€‡D7پ پQ7†€€€€€€€€€€€€€€€€€€€€€€€€€€€€ˆ€€€€€€€€WD7 ،
، †€€‡ پ پ پپپپپپپپ ،
، /RD€€€‡<>پ پ پ پپپپپپپپ ،
، DIR1€€‡OEپ پ پ پپپپپپپپ ،
، „€€‰€€€€‰€€… پپپپپپپپ ،
، ëز1533لً6 ëز1533éٍ23 پپپپپپپپ ،
، ‚€€ˆ€€€€ˆ€€ƒ ‚€€ˆ€€€€ˆ€€ƒ پپپپپپپپ ،
، D0€€€€€€‡D0پ RG پQ0†€€€€€€€€ˆ€€€€€€‡D0پ RG پQ0†€€€€€€€€… ،
، D1€€€€€€‡D1پ پQ1†€€€€€€€ˆ€€€€€€€‡D1پ پQ1†€€€€€€€… ،
، D2€€€€€€‡D2پ پQ2†€€€€€€ˆ€€€€€€€€‡D2پ پQ2†€€€€€€… ،
، D3€€€€€€‡D3پ پQ3†€€€€€ˆ€€€€€€€€€‡D3پ پQ3†€€€€€… ،
، D4€€€€€€‡D4پ پQ4†€€€€ˆ€€€€€€€€€€‡D4پ پQ4†€€€€… ،
، D5€€€€€€‡D5پ پQ5†€€€ˆ€€€€€€€€€€€‡D5پ پQ5†€€€… ،
، D6€€€€€€‡D6پ پQ6†€€ˆ€€€€€€€€€€€€‡D6پ پQ6†€€… ،
، D7€€€€€€‡D7پ پQ7†€ˆ€€€€€€€€€€€€€‡D7پ پQ7†€… ،
، †€€‡ پ پ پپپپپپپپ †€€‡ پ پ ،
، VCC€€‡<>پ پ پ پپپپپپپپDIR3€€‡WRپ پ پ ،
، /WR€€‡OEپ پ پ پپپپپپپپDIR2€€‡OEپ پ پ ،
، „€€‰€€€€‰€€… پپپپپپپپ „€€‰€€€€‰€€… ،
، پپپپپپپپ ،
، پپپپپپپ„€€€€€€€€€€€€€€€€€€€€€€€€€€€€WD8 ،
، پپپپپپ„€€€€€€€€€€€€€€€€€€€€€€€€€€€€€WD9 ،
، پپپپپ„€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€WD10 ،
، پپپپ„€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€WD11 ،
، پپپ„€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€WD12 ،
، پپ„€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€WD13 ،
، پ„€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€WD14 ،
، „€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€€WD15 ،
، ،
±                                                               µ
، ،
، "َبإخء, ×غة×ءإحءر × ًىي" ‚€€€€€€€€€€€€€€€€€€€€€DIR3 ،
، پ ‚€€ƒ ،
، ‚€€€/HDD_ENABLE€€€€€ˆ€‰€€€‡1 †€€€€€€€€€€/HDD_CS1 ،
، پ ‚€€ƒ پ ‚€€€‡ پ ،
، †€‡1 †€€€€€ƒ پ پ †€€‡ ،
، /WR€€€€€€€€€€پ€‡ پ پ †€پ€€€‡1 †€€€€€€€€€€/HDD_CS3 ،
، پ †€€‡ پ پ پ ‚€‡ پ ،
، †€‡1 †€€€ƒ پ پ پ پ „€€… ،
، /RD€€€€€€€€€€پ€‡ پ پ پ پ پ „€€€€€€ƒ ،
، پ „€€… پ پ پ پ ‚€€ƒ پ ،
، „€€€€€€ƒ پ پ ‚€€€€€€پ€‰€€€‡1 o€… ،
، پ پ پ پ پ „€€… ،
، پ پ پ پ پ ،
، ‚€€ƒ ‚€€ƒ پ پ پ پ †€€€€€€€€€€€€ƒ ،
، /WR€€€‡& †€€€€€‡1 †€… پ پ پ پ پ ،
، /RD€€€‡ پ ‚€‡ پ پ پ پ پ ‚€€ƒ پ ،
، „€€… پ „€€… پ پ پ „€€€€€‡1 پ پ ،
، پ پ پ پ ‚€€€€€€€€€€‡ †€ƒ پ ،
، پ پ پ پ پ WRH „€€… پ پ ،
، پ ‚€€ƒ پ پ پ پ ‚€€ˆ€€€€ˆ€€ƒ پ پ ‚€€ƒ ،
، A8€€€€€€ˆ€€€€پ€‡1 o€€€پ€پ€پ€‡ ‡S پ TT پ پ پ „€‡1 †€€€€€DIR2 ،
، پ پ „€€… پ پ پ پ †€€‡ پ Q†€€پ€€€‡ پ ،
، پ „€€€€€€ƒ پ پ پ †€‡D پ پ پ پ †€€‡ ،
، پ ‚€€ƒ پ پ †€پ€ٹ€>C پ پ _پ „€€€‡1 †€€€€€DIR1 ،
، /IO€€€€€پ€€€€€€‡1 پ پ پ پ پ پ †€€‡ پ Qo€€€€€€‡ پ ،
، پ ‚€‡ †€… †€پ€پ€پ€‡R پ پ پ „€€… ،
، پ پ „€€… پ پ پ پ „€€‰€€€€‰€€… ‚€€ƒ ،
، پ „€€€€€€ƒ پ „€پ€پ€€€€€€€€€€€€€€€€€€€‡1 †€€/HDD_WR ،
، پ پ پ پ „€€€€€€€€€€€€€€€€€€€‡ پ ،
، پ پ پ پ „€€… ،
، پ پ پ پ ‚€€ƒ ،
، „€€€€€€€€€€€پ€پ€€€پ€€€€€€€€€€€€€€€€€€€€€‡1 پ ،
، پ „€€€پ€€€€€€€€€€€€€€€€€€€€€‡ †€€/HDD_RD ،
، پ پ „€€… ،
، ‚€€ƒ ‚€€ƒ پ پ ‚€€ƒ ،
، A1€€€€‡& o€€€€€‡& o€… پ A0€€€€€€€€‡1 †€€€€€€€€€€€€€HD_A0 ،
، A2€€€€‡ پ ‚€€€‡ پ پ †€€‡ ،
، †€€‡ پ ‚€‡ پ پ A1€€€€€€€€‡1 †€€€€€€€€€€€€€HD_A1 ،
، A5€€€€‡1 †€… پ „€€… پ ‚€€€‡ پ ،
، A7€€€€‡ پ پ پ پ †€€‡ ،
، „€€… پ پ A2€€€€پ€€€‡1 †€€€€€€€€€€€€€HD_A2 ،
، A6€€€€€€€€€€€… پ †€€€‡ پ ،
، پ پ „€€… ،
، ‚€€ƒ ‚€€ƒ پ پ ،
، A1€€€€‡1 †€€€€€‡& †€€€€€€€پ€€€€€€€€… ،
، A2€€€€‡ پ ‚€€€‡ پ پ ،
، „€€… پ †€€‡ پ ،
، A14€€€€€€€€‰€€€‡& †€€€€€€€… ،
، A2€€€€€€€€€€€€€‡ پ ،
، „€€… ،
،                                                               ،
، ْؤإسط ذزدزةسد×ءخر شدجطثد جداةثء × ًىي. ،
، نإتسش×ةشإجطخءر زإءجةعءأةر × ثدزخإ دشجةقءإشسر دش خءزةسد×ءخخدت, ،
، شءث ثءث ًىي ذدع×دجرإش زإءجةعد×ظ×ءشط سجدضخظإ ئصخثأةة خء دؤخدت ،
، رقإتثإ. ëزدحإ شداد, ءؤزإسءأةر ذدزشد× ذزدةع×دؤةشسر قإزإع سبإحص ،
، زءسذزإؤإجإخةر ذدزشد× Sprinter-ء, ثدشدزءر ذدع×دجرإش ةعحإخةشط ،
، ×سإ ءؤزإسء ذدزشد× ×ةخقإسشإزء. ،
، ًزة ذد×شدزإخةة ؤدسشءشدقخد ذد×شدزةشط شدجطثد جداةثص ة دآإسذإقةشط،
، دشسصشسش×ةإ "اجةشقإت". ،
، ëزدحإ شداد × ًىي ××إؤإخء ؤدذدجخةشإجطخءر عءؤإزضثء دش خءقءجء /IO،
، شءث ثءث × زإضةحإ TURBO خء 21MHz خإ صسذإ×ءہش صسشءخء×جة×ءشطسر ،
، ءؤزإسء ذدزشد× ×ةخقإسشإزء. ،
، ÷ظ×دؤظ /HDD_WR,/HDD_RD,/HDD_CS1,/HDD_CS3 ذدؤءخظ خء IDE زءعكإح ،
، قإزإع سدذزدشة×جإخةر 150 دح. ،
، َةاخءج /HD_RES حدضخد ذدؤثجہقءشط, حدضخد خإ ذدؤثجہقءشط ث سآزدسص ،
، ثدحذطہشإزء. ىصقغإ خإ ذدؤثجہقءشط, خد خإثدشدزظإ ×ةخقإسشإزظ ،
، حداصش سإزطإعخد "عءشظثءشطسر" ذزة خإذزء×ةجطخدت زءآدشإ س خةحة ة ،
، ةح حدضإش ذدخءؤدآةشطسر ضإجإعخظت سآزدس. ،
، ء سةاخءج /PDIAG ×إغءإشسر س×إشدؤةدؤ قإزإع زإعةسشدز 300 دح خء ،
، +5v ؤجر ةخؤةثءأةة زءآدشظ HDD. (خد ةخداؤء س×إشدؤةدؤ س×إشةشسر ،
، ثءث ذدذءجد, دسدآإخخد سد سشءزظحة ×ةخقإسشإزءحة ة × زإضةحإ SLAVE ،
، َةاخءج /HD_RDY جةآد ذدؤثجہقءإشسر, جةآد خإ ذدؤثجہقءإشسر خء ،
، /WAIT ذزدأإسسدزء. ىصقغإ ذدؤثجہقةشط قإزإع ـجإحإخش é س سةاخءجدح ،
، ةؤصفةح خء ـشدش ×ظ×دؤ ذزدأإسسدزء سد سبإحظ ثدحذطہشإزء. ،
،                                                               ،
، ٍءع×دؤثء 40-pin زءعكإحء HDD ،
، ‚€€€€€€€€€€ˆ€€€€€€€ˆ€€€€€€€€€€ˆ€€€€€€€€€€€ƒ‚€€€€€€€€€€€€€€€€ƒ ،
، پ1 /HD_RESپ11 WD3 پ21 --- پ31 --- پپ پ ،
، پ2 GND پ12 WD12پ22 GND پ32 --- پپ "غشظزة" پ ،
، پ3 WD7 پ13 WD2 پ23 /HDD_WRپ33 HD_A0 پپ خء ذجءشإ پ ،
، پ4 WD8 پ14 WD13پ24 GND پ34 --- پپ ؤجر ثءآإجر پ ،
، پ5 WD6 پ15 WD1 پ25 /HDD_RDپ35 HD_A1 پپ پ ،
، پ6 WD9 پ16 WD14پ26 GND پ36 HD_A2 پپ 246 40 پ ،
، پ7 WD5 پ17 WD0 پ27 /HD_RDYپ37 /HDD_CS1پپ ooo........o پ ،
، پ8 WD10 پ18 WD15پ28 --- پ38 /HDD_CS3پپ ooo........o پ ،
، پ9 WD4 پ19 GND پ29 --- پ39 /PDIAG پپ 135 39 پ ،
، پ10 WD11 پ20 --- پ30 GND پ40 GND پپ پ ،
، „€€€€€€€€€€‰€€€€€€€‰€€€€€€€€€€‰€€€€€€€€€€€…„€€€€€€€€€€€€€€€€… ،
،                                                               ،
، َبإحء زءآدشءإش خء Sprinter-إ, خد × سءحدح زةسصخثإ ×دعحدضخظ ،
، خإشدقخدسشة. ،
،                                        ¸                      ،
، ًدزشظ HDD: xx50h..xx55h ، َقةشظ×ءخةإ سإثشدزء: ،
، ، CALL HDD_READY ،
، xx50h - ذدزش ؤءخخظب ، JR C,ERROR ،
، 0051h - ذدزش دغةآدث/ذزإؤثدحذإخسءأةة ، LD BC,0050h ،
، 0052h - ذدزش قةسجء سإثشدزد× ، INI..INI ; 512 زءع ،
، 0053h - ذدزش خدحإزء سإثشدزء ، RET ،
، 0054h - ذدزش خدحإزء أةجةخشزء, حجءؤغإاد ±                      ،
، 0055h - ذدزش خدحإزء أةجةخشزء, سشءزغإاد ، ْءذةسط سإثشزء: ،
، 4052h - ذدزش ؤزءت×ء/خدحإزء ادجد×ثة ، CALL HDD_READY ،
، 4053h - ذدزش ثدحءخؤ/زإاةسشزء سدسشدرخةر ، JR C,ERROR ،
، 4054h - ذدزش ذدزش 3F6h ، LD BC,0150h ،
، 4055h - ذدزش ذدزش 3F7h ، OUTI..OUTI ; 512 زءع ،
، ، RET ،
،                                        »                      ،
±                                                               µ
، ëءث زءآدشءإش سبإحء? ،
، ،
، Z80 ‚€€€ƒ ،
، bus پBufپ ،
، €€ˆ€€‡<€>†€€€€€€€€€€€€ˆ€€<€> Low Byte ،
، پ پ 1 پ پ ،
، پ †€€€‡ ‚€€€ƒ پ ،
، پ پBufپ پRegپ پ ،
، „€€‡€€>†€€ˆ€€‡€€>†€€… HDD bus ،
، پ 2 پ پ پ 3 پ ،
، „€€€… پ „€€€… ،
، پ ،
، „€€€€€€€€€€€€<€> High Byte ،
، ،
، 1. ‏شإخةإ ×سإب زإاةسشزد×, ثزدحإ زإاةسشزء ؤءخخظب, A8 = 0 ،
، نءخخظإ س غةخظ HDD قإزإع آصئإز 1 ذإزإؤءہشسر × ذزدأإسسدز. ،
، ôدجطثد حجءؤغةت آءتش, سشءزغةت خإ خصضإخ. ،
، ،
، 2.1 ‏شإخةإ زإاةسشزء ؤءخخظب, A8 = 0 ،
، نءخخظإ س غةخظ HDD قإزإع آصئإز 1 ذإزإؤءہشسر × ذزدأإسسدز. ،
، ôدجطثد حجءؤغةت آءتش, سشءزغةت خصضإخ ة دخ عءفإجثة×ءإشسر × ،
، زإاةسشزإ 3 ،
، ،
، 2.2 ‏شإخةإ زإاةسشزء ؤءخخظب, A8 = 1 ،
، نءخخظإ ةع زإاةسشزء 3 قإزإع آصئإز 1 ذإزإؤءہشسر × ذزدأإسسدز. ،
، - سشءزغةت آءتش - HDD × ـشدش حدحإخش خإ ×ظآةزءإشسر ،
، ،
، 3. ْءذةسط ×سإب زإاةسشزد×, ثزدحإ زإاةسشزء ؤءخخظب, A8 = 1 ،
، نءخخظإ س غةخظ Z80 قإزإع آصئإز 1 ذإزإؤءہشسر خء غةخص HDD. ،
، ôدجطثد حجءؤغةت آءتش, سشءزغةت خإ خصضإخ. ،
، ،
، 4.1 ْءذةسط زإاةسشزء ؤءخخظب, A8 = 0 ،
، نءخخظإ س غةخظ Z80 قإزإع آصئإز 2 ذإزإؤءہشسر × زإاةسشز 3. ،
، ôدجطثد حجءؤغةت آءتش, سشءزغةت خصضإخ ة دخ دضةؤءإشسر × سجإؤصہفإح ،
، أةثجإ. HDD × ـشدش حدحإخش خإ ×ظآةزءإشسر. ،
، ،
، 4.2 ْءذةسط زإاةسشزء ؤءخخظب, A8 = 1 ،
، نءخخظإ ةع زإاةسشزء 3 ذإزإؤءہشسر خء غةخص HDD - حجءؤغةت آءتش. ،
، - سشءزغةت آءتش - قإزإع آصئإز 2 ذإزإؤءإشسر س ذزدأإسسدزء ،
، ،
، ًدقإحص ذصخثش 4.2 دشجةقءإشسر دش 3, بدشر دذإزءأةة ذد ×ةؤص ،
، دؤةخءثد×ظ? ،
، ًدشدحص قشد ذإزإؤ 4.2 ×سإاؤء ةؤإش 4.1, ثدشدزظت صسشءخء×جة×ءإش ،
، شزةاإز WRH × إؤةخةأص ة, شءثةح دآزءعدح ذإزإثجہقءإش ذصشط ،
، ذزدبدضؤإخةر آءتشد×. üشد ة ذدع×دجرإش ةسذدجطعد×ءشط ثدحءخؤظ OUTI ،
، ؤجر عءذةسة سإثشدزء × HDD ،
، ،
«                                                               ®
=== Cut ===

÷ءت! ًزدشدسظ ءشءثصہش حدةب عإزجةخاد×! ًدزء سحءشظ×ءشطسر. Ivan.

- ٍءع×دؤةسط سبإحثء, آدجطغء ة حءجإخطثء.. [ Sprinter-II ] [Forth-CPU] [ZX]

... E-mail: ivan...@mail.ru * Welcome to www.atlant.ru/peters *

7 Sep 1999 you wrote here:

IM> This long-awaited day has come!

Hurray! ;)

IM> Scheme of Sprinter's HDD!
[...]

Excellent. Is there a blocker for IS-DOS with a customizer for it? If there is one, throw it in!

IM> · In addition, an additional delay has been introduced into the PLM from the beginning of /IO·
IM> · since in TURBO mode at 21MHz there is no time to set ·
IM> · hard drive port addresses. ·

How much time is normalized for this?

IM> · The /HDD_WR,/HDD_RD,/HDD_CS1,/HDD_CS3 pins are fed to the IDE connector ·
IM> · through a 150 ohm resistance. ·

Here Kirill Frolov once said that such resistors in the Nemovsky
controller serve to “increase the mass of the product.” Please, if possible, briefly
explain their necessity.

[accidentally skipped about the fact that /HD_RDY can be set to /WAIT, or not]

How is that? Explain this matter in more detail. Will this be important when writing software? And
do all IDE screws have this signal?

5 Sep 1999 you wrote here:

SK> I also wanted to assemble Nemovskaya, but recently the
SK> question began to torment me: is
SK> not such a weak decryption of the ports of this
SK> circuit dangerous for the information on the screw?
SK> For me, the safety of information is the main priority.

No I know, so far everything is fine.
The scheme is old, if there was something wrong, they would have noticed.
And in order to get to the information on the screw, you need to go through more than one register
...

And besides this, the exchange speed is also important.

SK> Moreover, I decided to make the ports of all peripherals available both in SOS and
in
SK> DOS (with the exception of VG93 and BB55).

Come on, give birth to another standard. ;)

By the way, apparently, ZX-Next's scheme satisfies all your requirements
+ and is also the fastest after Sprinter's.

SK> I think we need to make 16-bit ports: the low byte is the port number
SK> of the screw controller, the high byte is for selecting the internal registers of the HDD. At the same time, the
SK> circuit should not be more complicated than Nemov's.

Sprinter's value is not suitable...

SK> Strictly, I only need the port number and the optimal location of
bits
SK> control.

Keep ZX-Next's ones. (very skipped)

SK> On the same board with the controller, I am going to place the circuit
SK> CMOS clock using GLUK without using the #EFF7 port.

It’s the owner’s business.
AWhat about "top priority"? ;)

╒═════════ hddinfo .W ════════════──
Brief description of ports and bits of the hard drive controller.
(C) Slot & Co
(R) Valerij Kozhevnikov (500:95/462.18@ZXNet)
[...]
┌───────┬────────── ─────────────────┬──────── ─────────────────────┐
│ │ IN │ OUT │
╞═══════╪════════════════════════
│ #FDAF │ Data register D8-D15 │ not used │
│ #FFAF │ not used │ Data register D8-D15 │
│ #FEAF │ Data register D0-D7 │ Data register D0-D7 │
│ #F6AF │ Error register │ Precompensation register │
│ #EEAF │ Sector Counter Register │ Sector Counter Register │
│ #E6AF │ Sector Number Register │ Sector Number Register │
│ #DEAF │ Cylinder Number Register │ Cylinder Number Register │
│ │ (low) │ (low) │
│ #D6AF │ Cylinder number register │ Cylinder number register │
│ │ (high) │ (high) │
│ #CEAF │ Accumulator/head register│ Accumulator/head register │
│ #C6AF │ Status register │ Command register │
├───────┼────────────────────────
│ #CAAF │ Alternate register│ Managing the storage │
│ │ drive status │
│ #C2AF │ Drive address register │ not used │
└───────┴──────── ───────────────────┴─── ──────────────────────────┘

[...]
However to speed up I/O operations, the port addresses are located in such a way that it is possible to use the INI-
/OUTI commands.

for example, reading one word:

LD HL,BUFFER
LD BC,#FEAF
INI
INI

or writing:

LD HL,BUFFER
LD BC,#00AF
OUTD
OUTI

* Address #00AF is taken due to the fact that the OUTI command does DEC B
before forwarding to the port.

[...]

Addressing HDD IDE registers.
To address HDD IDE registers in ZXNEXT, the following signals are used:
A5,A6,A7,A8,A9 - (selecting lines) form the base address
registers HDD.
A10,A11,A12,A13 - (address lines) are used when selecting
HDD registers.
/WR - strobe for writing data to registers.
/RD - strobe for reading data from registers.
To select registers:
A5,A7,A9 = 1
A6,A8 = 0
The status of other signals is shown in table.

┌─────┬─────┬─────┬─────┬───
│ A10 │ A11 │ A12 │ A13 │ Read registers │ Write registers │
│ │ │ │ │ by signal /RD │ by signal /WR│
╞═════╪═════╪═════╪═════╪══════════════════╪══════════════════╡
│ 0 │ 0 │ 0 │ 0 │ #C2AF │ - │
│ 0 │ 1 │ 0 │ 0 │ #CAAF │ #CAAF │
│ 1 │ 0 │ 0 │ 0 │ #C6AF │ #C6AF │
│ 1 │ 1 │ 0 │ 0 │ #CEAF │ #CEAF │
│ 1 │ 0 │ 1 │ 0 │ #D6AF │ #D6AF │
│ 1 │ 1 │ 1 │ 0 │ #DEAF │ #DEAF │
│ 1 │ 0 │ 0 │ 1 │ #E6AF │ #E6AF │
│ 1 │ 1 │ 0 │ 1 │ #EEAF │ #EEAF │
│ 1 │ 0 │ 1 │ 1 │ #F6AF │ #F6AF │
│ 1 │ 1 │ 1 │ 1 │ #FEAF │ #FEAF │
└─────┴─────┴─────┴─────┴──────────────────┴──────────────────┘

╘═════════ end of file ════════════──

Some
inaccuracies were discovered in the HDD diagram that I sent a few days ago.
1. The DIR1 and DIR2 signals are swapped.
2. The HD_A0 and HD_A1 signals on the HDD connector wiring are swapped! Wow! The Protoss are attacking my Zerlings! It's time to get going. Ivan.

- Divorce the circuit, big and small.. [ Sprinter-II ] [Forth-CPU] [ZX]

RM> Here Kirill Frolov once said that such resistors in the
RM> Nemov controller serve to “increase the mass of the product.” Please, if
RM> it is possible, briefly justify their necessity.
These are “anti-ringing circuits”. If they are not there, some hard drives catch two
write/read pulses instead of one without them. There are hard drives that work perfectly
without them.

RM> [accidentally skipped about the fact that /HD_RDY can be started on /WAIT, but
RM> it can not]
RM> How is that? Explain this matter in more detail. Will this be
RM> important when writing software? And do all IDE screws have this signal?
This is a solid signal. If the computer does not have a TURBO mode, it may not be needed. Because the time required to access the HDD will obviously be longer than necessary (according to the standard - 280-420ns). If there is TURBO, then it is better to start this signal. And it’s better through a buffer, so that interference from the cable doesn’t creep in.

RM> The sprint rating is not suitable...

EVERYTHING!!! I recently received the Sprinter scheme.
After checking it (theoretical) and correction, I will do it.
I liked the idea of ​​​​using automatic commands INI, OUTI
The DOS state is not taken into account.
The decoding is stronger.

So it’s suitable.

RM> Keep the ZX-Next ones. (much skimmed)

I have it.

IM> This is an iron signal. If the computer does not have TURBO mode, then it may not
IM> be required. Because the time required to access the HDD will obviously be longer
IM> than necessary (According to the standard - 280-420ns). If there is TURBO, then it is better to turn on this
IM> signal. And it’s better through a buffer, so that interference from the loop doesn’t creep in.

You didn’t understand me. Do all IDE screws have this signal _active_? I somewhere
saw information that this is an EIDE signal.
And if this signal is set to /WAIT, does this mean that somewhere in the driver
the “Data Request” bit may not be controlled?

September 13, 1999, Sergey Karachentsev writes to Roman Milukov:

SK> EVERYTHING!!! I recently received the Sprint scheme.
SK> After checking it (theoretical) and correction, I will do it
SK>.

Why check it? It has been working properly for a couple of years...

Best regards,
Renat

Wow! The Protoss are attacking my Zerlings! It's time to get going. Ivan... data-saferedirecturl="https://www.google.com/url?hl=ru&q=http://www.atlant.ru/peters&source=gmail&ust=1785433330524000&usg=AOvVaw0dS1H0GoWjqNAeqw088hP3">www.atlant.ru/peters *

SK> Which one? I don’t understand...

You left out your statement “for me the main priority is the safety of information.”
#EFF7 in the watch was designed specifically for the safety of information, as far as I know.

RM>>> maybe not]
RM> You didn’t understand me. Do all IDE screws have this signal _active_?
Not all of them. Therefore, it is not always necessary to start it.

RM> I saw somewhere that this is an EIDE signal. And if this signal is set to
RM> /WAIT, does this mean that in some places in the driver the
RM> “Data Request” bit may not be controlled?
This signal is not connected with “Data Request”. This signal is used to extend the read/write cycle until the required time. In non-turbo mode, this extension
is usually not required.

What is the best HDD controller circuit to assemble?

I know three circuits:
1. Nemo's [ZXF8]
2. ZXNet's
3. Sprinter's
(What other circuits have been invented? Who knows?)

At first I wanted to assemble circuit (1) because of its simplicity. But since it takes up a quarter of the port address space, I was forced to look for an alternative. A large number of addressable ports is undesirable not only because
the probability of accidentally hitting them increases, but also because many
port addresses are already occupied by other peripheral devices invented to
the present time.
The only reasonable method to combat this phenomenon is to LIMIT the address
port space used in each PU. This means that it is advisable, if possible, to use the most significant
byte SHA to address the internal ports (registers) of the PU. And for decrypting the PU ports as a whole - the low byte SHA,
decrypted completely (this is in many cases easily achieved by installing IC LA2 on the PU with all the lines that should be in “1”, including /M1).
Scheme (2) is suitable for these requirements. All its ports have the number #AF in the low byte. But this scheme includes nodes that provide additional
functions not related to the HDD. The circuit assembled without these nodes will behave
redundancy. And yet, most users want to assemble the HDD controller and make it as simple as possible. I wanted to combine the simplicity of the circuit (1) and a good decoding of the circuit (2), but then I decided to do it my own way.
Recently I saw the circuit (3) in the echo. This scheme has an additional
possibility. It allows you to use automatic input/output commands.
That is why I decided to build this circuit. But in the process of checking, I discovered that the circuit published in the echo CANNOT work normally (the control unit on
TM2 does not allow simultaneous output of DIR1 and DIR2 signals, which means it is impossible
reading from the IR23 register). Any attempts to eliminate this error lead to
complication of an already complex circuit. For Sprinter owners, this has
no significance since the entire circuit is built into a compact PLM. But I want to assemble a circuit without any PLM, using all available logic. And therefore, simplification of the circuit is
one of the main issues.
If we abandon compatibility with Sprinter, then the circuit can be simplified
quite greatly. At the same time, the advantages of the original will remain. To get
a driver for a simplified scheme, it will be enough to enter new port addresses into
the existing Sprinter driver.
So, my idea:
- remake the control circuit
- leave the buffer circuit unchanged - add it to the boardCMOS clock based on
GLUK (without complicating the circuit)
- add an IOGE signal conditioner
- move the HDD register selection lines to the high byte ША
- add to the low byte the data transmission mode line through the controller
One of the possible bit layout options:
A0...A3,A5,A7 - must be in "1"
A4 - data transmission mode bit
A6 - must be "0"
A8 - data passage mode bit
A9...A11 - HDD register selection bits
A12 - CS0_HDD/CS1_HDD selection bit
In this case, the circuit forms ports #XXAF and #XXВF.
ports #XXAF - for access to the HDD data register
ports #XXBF - for access to other HDD registers

What other ports can be used ?
Which ports should the IOGE signal block? (port numbers)

After unequivocally solving all the issues, I will assemble the HDD controller.
I’ll upload the circuit diagram into the echo.

Sincerely, Sergey Karachentsev.

Once, Wed Sep 22 1999 11:55, Sergey Karachentsev wrote to All about [HDD &
SPECCY]:

SK> I know three schemes:
SK> 1. Nemo's [ZXF8]
SK> 2. ZXNet's
SK> 3. Sprinter's
SK> (What other circuits have been invented? Who knows?)

SK> At first I wanted to assemble circuit (1) because of its simplicity. But since
SK> it takes up a quarter of the address space of the ports, I was forced
SK> to look for an alternative.

It was possible to find out what addresses the drivers use and do a complete
decryption (8 occupied ports).

SK> not only because the probability of accidentally hitting
SK> them increases, but also because many port addresses are already occupied by other
SK> peripheral devices, invented up to the present
SK> time.

but this is worse:(
name the conflicts.

SK> This means that it is desirable, if possible, to use the high byte SHA for addressing the internal
SK> ports (registers) of the PU.

for a screw this is fatal - the access speed will drop (unless, of course,
you use perversions, as in scheme 3; of course, from the point of view of construction, this is
the best scheme).
but in general - the most competent recommendation.

[skipped]

SK> register IR23). Any attempts to eliminate this error lead
SK> to complicating the already complex circuit. Forfor Sprinter owners this does not
SK> have any significance since the entire circuit is built into a compact PLM. But
SK> I want to assemble a circuit without any PLM, using all available logic. And
SK> this is why simplifying the circuit is one of the main issues. If
SK> we give up compatibility with Sprinter, then the scheme can be simplified quite
SK> greatly.

but tell me, why the hell is this compatibility? there is almost no software, and if there is,
then you need sprint memory and everything else.

SK> A0...A3,A5,A7 - must be in "1" A4 - passing mode bit
SK> data A6 - must be "0" A8 - passing mode bit
SK> data A9...A11 - HDD register selection bits A12 - selection bit
SK> CS0_HDD/CS1_HDD In this case, the circuit forms ports #XXAF and
SK> #XXВF.

#BF I don’t recommend it, there’s something standard hanging on it, I don’t remember what exactly.

SK> What other ports can be used?

let’s say, change A7, A5 and A0 in your configuration to “0”. we will get #0E and #1E,
there will definitely be no conflicts (no one would think of choosing such ports,
for some reason everyone loves ones on address lines). There won’t be any special glitches when there is no
device and you try to start the driver - at most the border
will change.

SK> Which ports should the IOGE signal block? (port numbers)

only those needed by yourdevice.

All the best.
Dmitry.

... LD..X-TRADE... [ZX]

On Sergey Karachentsev wrote All:

SK> 3. Sprinter's
[skip]
SK> Recently in the echo I saw diagram (3). This circuit has
SK> an additional feature. It allows you to use automatic
SK> I/O commands. This is why I decided to collect this circuit. But in the
SK> verification process, I discovered that the circuit published in the
SK> echo CANNOT work normally
[skip]
There really is an error. I am posting the corrected version of the diagram in the following letter.
(One element “2I” has been added.)

Wow! The Protoss are attacking my Zerlings! It's time to get going. Ivan... data-saferedirecturl="https://www.google.com/url?hl=ru&q=http://www.atlant.ru/peters&source=gmail&ust=1785433330530000&usg=AOvVaw3wTls7TfY2UWCFdWnl7RTz">www.atlant.ru/peters *

DL>> #0E and #1E, there will definitely be no conflicts (no one would think
DL>> to choose such ports, for some reason everyone loves ones on address
DL>> lines).
IM> In Sprinter, port #1E is occupied. Internal processor port...

zanu. but this is not about the Sprinter, but about the ideology of the controller that you created in it. this will be installed on a regular computer.

IM> You can find a smaller PLM and get everything you need quite cheaply and
IM> with a minimum of cases.

PE3 or what? :-/
In artisanal conditions, this is not an option.

IM> In addition, in new developments where PLMs are used, this scheme can
IM> be introduced immediately.

And yes, yes, of course.

4. Profakovskaya
5. Turbo-2+'ovskaya
+ a bunch of all sorts of unknown original options.

...
SK> Scheme (2) fits these requirements. All its ports have the number #AF in the low
byte
SK>. But this circuit includes nodes that provide additional
SK> functions not related to the HDD.

If you throw out everything unnecessary from it, retaining only the logic of working with the HDD, then
it will be no more than Nemov’s.

To ALL: Someone please give me an official driver for the ZX-Next by Slot ports! PLEASE!

DL> say, change A7, A5 and A0 in your configuration to “0”. we will get #0E and #1E,
DL> there will definitely be no conflicts (no one would think of choosing similar
DL> ports, for some reason everyone loves ones on address lines). special glitches with

Love for units is not an accidental phenomenon. This is exactly how the ports in the branded SPECTRUM were built. Each bit was responsible for its own device. Then
SPECTRUM had few peripherals and that's why there were enough bits. Now there are so many peripherals that it’s time to forget about simplified decoding. If you don't want to have problems with upgrades in the future, then install full decryption on all ports as soon as possible. I have already done this for myself.
But in this case, choosing ports with a large number of units is more convenient because
such a port is easier to decrypt. The industry does not produce multi-input "OR" microcircuits, but "AND" ones are available, for example K1533LA2 (8-AND-HE).
Since I am going to make another CMOS clock on the HDD controller board, it is better to
choose ports with the largest possible number of matching bits.
For port #F7, the simplest circuit is obtained if you use ports with one
one reset: #FE, #FD, #FB, #EF, #DF, #BF, #7F.
Of these, only #DF and #BF can be used
For example #DF:
#F7 1 1 1 1 0 1 1 1CMOS clock
#D7 1 1 0 1 0 1 1 1 HDD data register
#DF 1 1 0 1 1 1 1 1 Other HDD registers

You can abandon the GLUK CMOS ports. Then the choice will be much
richer.

To simplify the CMOS circuit, you can also abandon the CMOS blocking port
(#EFF7).
Who knows why this port is needed at all?

DL> in the absence of a device and trying to start the driver will also not work - at most
DL> the border will change.

DL>> #0E and #1E, there will definitely be no conflicts (no one would think
DL>> to choose such ports, for some reason everyone loves ones on address
DL>> lines). special glitches with

SK> Love for units is not an accidental phenomenon. This is exactly how ports were built in
SK> branded SPECTRUM. Each bit was responsible for its own device. Then
SK> SPECTRUM had few peripherals and there were enough bits for that. Now there are so many peripherals that it’s time to forget about simplified
SK> decryption. If you don’t want to have problems with upgrades in the future, then
SK> install full decryption on all ports as soon as possible. I have already done this for myself
SK>. But in this case, choosing ports with a large number of
SK> units is more convenient because such a port is easier to decrypt. The industry does not
SK> produce multi-input “OR” microcircuits, but there are “AND” ones, for example
SK> K1533LA2 (8-AND-HE).

competent answer ;)
can’t we put in an extra LL1? something so scarce? When you arrive, I’ll pour in 50 of them :-)

SK> To simplify the CMOS circuit, you can also dispense with the
SK> CMOS blocking port (#EFF7). Who knows why this port is needed at all?

to reduce the likelihood of getting into the watch. there is a locking bit there.

SK>>> CMOS locks (#EFF7). Who knows why this port
SK>>> is needed at all?
DL>> to reduce the likelihood of hitting the watch. there is a locking
DL>> bit.
SK> If this is the only function of this circuit, then there is no point in it.
SK> This probability needs to be reduced by increasing the degree of decryption of the ports, and
SK> not by piling up all sorts of locking bits.

The author of this scheme, apparently, was an extremely careful person
(and incredibly modest) that he was embarrassed to release into the wild such a genie.
moreover, in the author’s implementation, I remember hanging cs on the ground would lead
to an increase in energy consumption (mb and load on the bus).

Sincerely,
Renat

Wow! The Protoss are attacking my Zerlings! It's time to get going. Ivan... data-saferedirecturl="https://www.google.com/url?hl=ru&q=http://www.atlant.ru/peters&source=gmail&ust=1785433330539000&usg=AOvVaw1SNnoRc9qOTMPvnKuHVJTw">www.atlant.ru/peters *

As a result of numerous simplifications, a circuit was obtained on 13 ICs
(including a CMOS clock).

The circuit has:
- complete decoding using the low byte SHA
- full CMOS clock interface using GLUK
- IOGE signal generation circuit
- support for automatic input/output commands
(similar to the HDD controller Sprinter)
- uses only one port to access the HDD
(by the low byte SHA)

The scheme allows you to use Sprinter and ZXNet HDD drivers
by simply replacing the port numbers.

At the moment, the HDD port number has not yet been determined.
This scheme allows you to use a port number containing no more than
three (3) zeros. In the case of the maximum number of zeros (3), one of them
must be D3 (corresponding to port #F7).

There is a suggestion: use port #AF (ZXNet)

Who has a different opinion?

Regards, Sergey Karachentsev.

27 Sep 1999 you wrote here:

SK> As a result of numerous simplifications, a circuit with 13 ICs
SK> (including CMOS clock) was obtained.
...
SK> The circuit allows you to use HDD Sprinter and ZXNet
SK> drivers by simply replacing the port numbers.

And these are the drivers no! ZX-Next's is not available, and Sprinter's is not available at all. So you will have to write from scratch.

SK> At the moment, the HDD port number has not yet been defined.
SK> This scheme allows you to use a port number containing no more than
SK> three (3) zeros. In the case of the maximum number of zeros (3), one of them
SK> must be D3 (corresponds to port #F7).

SK> There is a suggestion: use port #AF (ZXNet)

No need! There will be an overlay on standard ZX-Next ports, and problems with
incomplete decoding of the Kondratiev scheme will come out.
Better take #BF.

IM> In general, it is best to install the EPM7032SLC44 ($4) and on it, in addition to the HDD
IM>, install
IM> something else you need. Or EPM3032ALC44, it’s cheaper ($2.24), but just

Do it. Install a HDD and a flop controller with HD mode on it.
Release the board so that it can be plugged into the KAI slot. You'll make Nemo very happy. ;)

...

RM> The author of this circuit, apparently, was an extremely cautious person
RM> (and incredibly modest) that he was ashamed to release such a genie into the wild.
RM> Moreover, in the author’s implementation, I remember hanging cs on the land would lead
RM> would
RM> to an increase in energy consumption (mb and load on the bus).

In my last version, I still decided to make a circuit CMOS with all
GLUK ports. Let the gin remain where it was :)

With respect, Sergey Karachentsev.

RM>> gin. Moreover, in the author’s implementation, I remember hanging cs on
RM>> land would lead to an increase in power consumption (mb and load
RM>> on the bus).

SK> In my last version, I still decided to make a CMOS circuit with all
SK> GLUK ports. Let the gin remain where it was :)

So I think that since the author intended it, that’s how it should be. I’ll tell the author to let him rejoice :)

Sincerely,
Renat

RM> No need! There will be an overlay on the standard ZX-Next ports, and problems with
RM> incomplete decoding of the Kondratiev scheme will come out.
RM> Better take #BF.

There is nothing terrible in this overlay, since no one will ever install
two HDD controllers at the same time, then the #AF port is already allocated for access to the HDD
and is used as such. And nothing is known about the #BF port. What if someone
connected a CD-ROM or something else through it.
Although for my scheme it doesn’t matter whether it’s #AF or #BF.

Sincerely, Sergey Karachentsev.

FK> Have you seen the temporary Z80? /IORQ appears *simultaneously* (!) with
FK> the /RD (or /WR) signal in the I/O cycle. Now I’ll tell you again:
FK> you need to form an interception /IOGE from “clean”
FK> addresses! That's it.

You'll have to personally find a book on the Z-80 and check it out.
If this is true, measures will be taken immediately.

Sincerely, Sergey Karachentsev.

Wow! The Protoss are attacking my Zerlings! It's time to get going. Ivan... data-saferedirecturl="https://www.google.com/url?hl=ru&q=http://www.atlant.ru/peters&source=gmail&ust=1785433330546000&usg=AOvVaw1CM2xDuEuEWR1WBGfCMhgY">www.atlant.ru/peters *