HALT

Here someone was interested in how the subject works.
So the Z80 reads the COP in each cycle and resets the memory.
Only it doesn’t care about the COP, it ignores it and NOP
performs it. That's what it says in the Zilog manual. There
by the way, the 'bugs' of the processor are described, in fact these
are not bugs, but features. And there is not a word about SLI and halves IX and IY!

15 Sep 00 00:59, Kirill Frolov -> All:

KF> Someone here was interested in how the subject works.
KF> So the Z80 reads the COP in each cycle and resets the memory.
KF> Only it doesn’t care what COP, it ignores it and NOP
KF> performs. That's what it says in the Zilog manual.

That's what I wrote... ;)

With respect, George aka -=GPV=-.

KF> Here someone was interested in how the subject works.
KF> So the Z80 reads the COP in each cycle and resets the memory.
KF> Only it doesn’t care what the COP is, it ignores it and NOP

16 Sep 00 23:54, Dmitriy Nesmachny wrote to Kirill Frolov:

DN> R increments every 4 bars?

Once for reading a cop with a refresh.

KF>> Here someone was interested in how the subject works.
KF>> So the Z80 reads the COP in each cycle and resets the memory.
KF>> Only it doesn’t care what the COP is, it ignores it and NOP
KF>> executes it. That's what it says in the Zilog manual. There

KF> Once for reading a cop with a refresh.

I understand what’s wrong with the refresh, but why isn’t it painted? (c) :-)))
Once again: when executing the HALT command, R is incremented every 4 clock cycles? Or in
another way: reading a KOP with a refresh takes place in 4 bars?

With respect, Dmitriy.

23 Sep 00 13:52, Dmitriy Nesmachny wrote to Kirill Frolov:

DN> Once again: when executing the HALT command, R is incremented every 4 clock cycles?

No. It is incremented 1 time at the time of refresh.

DN> Or in another way: reading the COP with a refresh in 4 clock cycles?

Yes.