GIF viewer for ZX.

Sunday October 13, 2002 at 19:29:00, Valerij Kozhevnikoff => All:

VK> GIF image viewer 1.0b 256x192 B&W
VK> (c) Jason 2002

VK> I look forward to your wishes and bug reports.

An excellent and very necessary program, often you come across various diagrams
in this format, but there is nothing to look at, now thanks to you, life will become
a little easier THANK YOU... As for wishes, well, of course, support for the upper
memory and the ability to cut out the desired piece... Of the bugs, everything seems to be ok
except that he doesn’t want to show some gifs, but these are probably just the ones
you mentioned.

Alexandr.

AT> An excellent and very necessary program, you often come across various
AT> circuits in this format, but there’s nothing to look at, now thanks to you, life will be
AT> a little easier THANK YOU... As for wishes, well, of course, support for upper
AT> memory and the ability to cut out the desired piece... Of the bugs, everything seems ok
AT> except that it doesn’t want to show some gifs, but that’s probably how since those
AT> that you mentioned.

There is only one serious bug. The amount of available lower memory
is determined with an error of 260*6=1560 bytes. If you look at wide pictures, the line buffer will creep onto the disk cache. This is what happens if you comment out an extra JR
...

1.1b is free of this drawback.
Now I will test the 512x192 version...

It works! Interlaced 512x384! People, remember this day - October 15, 2002! With the starting address of the program = 30700 in bare form (all
residents and the 64-character driver have been removed from memory) ISDOS version 3.5, the memory for the line buffer is
7460 bytes, and this is enough for images 1800 pixels wide! I just looked at the XTR
modem circuit, and this is 1084x784 pixels, and only 4472 bytes were
occupied!
I click on the screens every interruption. I'll make the /g+ key right now to enable gigascreen
.

* Original written in REAL.SPECCY
* also sent to ZX.SPECTRUM
* also sent to ZXNET.SOFT

WBR, Jason.

/*e-mail:jason2000(subject)yandex.ru ICQ: . 62235830*/

/np:/ *silence*

VK> There is only one serious bug. The amount of available lower memory
VK> is determined with an error of 260*6=1560 bytes.

VK> 1.1b is free of this drawback.

And where is it? Have you already fasted? Or is it still in progress?

VK> It works! Interlaced 512x384!
VK> I click the screens every interruption. I’ll make the /g+ key right now to turn on the gigascreen
VK>.

How to implement a gigascreen on Scorpio, port #eff7 is also available
512*192
what else needs to be soldered? schematic if possible.

By the way, I wanted to ask you once wanted to convert dosx to work together with the i8259 control panel, how are things going? or abandoned?

Alexandr.

VK>> turn on the gigascreen.
AT> How to implement a gigascreen on a scorpion, the #eff7 port is available
AT> also 512*192, what else needs to be soldered? schematic if possible.

Not necessary. Gigascreen doesn't make sense. Implemented in software
(switching screens every 224 clock cycles).

VK>> enable gigaskrin.

AT> How to implement gigaskrin on Scorpio, port #eff7 is also available
AT> 512*192 what else needs to be soldered? schematic if possible.

I lost the schematic, how I did it on Scorp.
Now I’ll restore it, looking at the board.

For the Pentagon, here it is.

_······------====== Monitor glass cutter ======------······_
GIGASCREEN!
I’m here a lot dem I looked again.
In many screens they blink to get more colors.
And then I thought.
-Why not do this in hardware.
And I did it using the interlace method, that is, the blinking
of the image stopped.
And bit 4 in port #EFF7 is free, so I used it hung up.

And here is the circuit for PENTAGON.

bit 3 #7ffd
SCR1──────────────────┐ 2┌──┬──┬──┐4
_____ 1┌─┬──┬─┐5 └──────┤A1│MX│Y1├─────INTELOUTSIDE
RESET ────┤R│TT│Q├───────┐ 3│ │ │ │
2│ │ │_│6 │ ┌──┤B1│ │ │
D4 ───────┤D│ │Q0─x │ │ 1├──┤D3│ │
___ 3│ │D1│ │ └───┼──┤AB│ │ │
SEL ──────┤C│ │ │ │15│__│ │ │
4│ │ │ │ ┌──┼──┤OE│ │ │
+5V <────┤S│ │ │ ─┴─ │ └──┴──┴──┘
└─┴──┴─┘ ┌───┐ │
3н D14 ────────────────┤=1 │ │
15600 Hz │ ├─┘
13┌─┬──┬─┐9 ┌┤D2 │
+5V <─────┤R│TT│Q├─x │└───┘
12│ │ │_│8 │
┌──┤D│ │Q0─o─┘ 25 Hz
KSI │11│ │D1│ │ │
10н D51 ─┼──┤C│ │ │ │
│10│ │ │ │ │
+5V <──┼──┤S│ │ │ │
│ └─┴──┴─┘ │
└───────────┘

Mikruhi.
--------
D1-1533 TM2
D2-1533 LP5
D3-1533 KP11

Explanations for the circuit.
-----------------
The SEL signal is the sampling signal of the #EFF7 port.
10n D62 needs to be cut off from the board.
The INTELOUTSIDE signal should go where 10n D62 went.

Now you can load demos that flashed screens
and enjoy the effect in full.

TO> Such a question, how can I attach all this to the Pro?

I’ll explain:
1) 10n D62 This is the output from port #7FFD of the signal to turn on the second
screen (on the Pro it’s called POLE_SCR).

2) 3n D14 This is the horizontal frequency.

3) 10n D51 This is the frame frequency impulse.
___
4) If your selection of port #EFF7 is not collected, then you will have to generate the SEL signal yourself.
I hope you know how to select port #EFF7.

_·····------====== Monitor glass cutter ======------······_

And this is how it was done for me, on green Scorpio. Port #EFF7 is assembled on TM9.
By the way, I don’t remember what I did with decoding, but it turned out to be less than in the case
in the known circuit, and no air conditioners are needed.

We need to cut off the signal going to 3n DD17.

bit 3 #7FFD 2┌──┬──┬──┐4
15n DD46A1│MX│Y1├───── 3n DD17
SCR 3│ │ │ │ (SCR came here)
┌──┤B1│ │ │
bit 4 #EFF7 │ 1├──┤D1│ │
│ │
┌──┼──┤OE│ │ │
─┴─ │ └──┴──┴──┘
┌───┐ │
3н DD5 ───────────┤=1 │ │
15600 Hz │ ├──────┘
┌────┤D2 │
3n DD7 ──────┘ └───┘
25 Hz

D1 - 1533 KP11
D2 - 1533 LP5

3n DD5 is a horizontal frequency, according to the scheme the signal V0.
3n DD7 is nowhere used.

bit 4 - GIGASCREEN.
Hardware interlace.
As you know, Spec has two screens, and each of them has 192
lines. The interlacing cycle takes two frames. In the first screen, even lines from the zero screen and odd lines from the first screen are displayed, in the second - odd lines from the zero screen and even lines from the first screen.
The effect is similar to when each interrupt switches the screen, but
without obvious flickering.
By the way, this bit can be used together with the 0th or 1st, interlacing
on the side how many colors or dots there are on screen.
_······------====== Monitor glass cutter ======------······_

I restored the circuit by looking at the board. If it doesn't work, write.

AT> By the way, I wanted to askyou once wanted to remake dosx to work together with the
AT> control panel i8259, how are things going? or abandoned?

Abandoned. I found out that this can be done and the interest disappeared. Kondratieff once made a mistake in that he tried to make all this work in IM2, which is impossible
due to the different interrupt acknowledge cycles of the 8259 and Z80 in this mode. In
IM0 it was necessary to do. 8259 simply slips the opcode CALL xxxx onto the bus, where xxxx
is determined during its programming... The document is in Russian, 15 kb zip.

WBR, Jason.

/*e-mail: jason2000(subtitle)yandex.ru ICQ: . 62235830*/

/np:/ *silence*

KF> No need. Gigascreen doesn't make sense. Implemented in software
KF> (switching screens every 224 clock cycles).

What the hell? When scrolling the image, you need to transfer 24 KB from the top jars down
and then into the 5th and 7th jars. While these 24 KB percents are shoveling, who will switch the screens every
224 clock cycles?
Now, when the gigascreen is turned off, its functions are performed by the 3rd bit
7FFD on interrupts... The screen flickers. Flickering is treated as follows:

GIGASCR_KEY
EXX
INC HL
INC HL
LD A,"+"
CP (HL)
RET NZ
LD HL,EXT_SW1+1
SET 4,(HL) ;enable
LD HL,EXT_SW2+1
RES 3,(HL) ;do not wave the screens
LD HL,EXT_SW3+1
RES 3,(HL)
RET

Three gradations of brightness per point: white, gray, black...

VK> Abandoned. I found out that this can be done and the interest disappeared. Kondratiev
VK> made the mistake of trying to make all this work in IM2, which
VK> is impossible due to the different interrupt acknowledge cycles of the 8259 and Z80 in
VK> that mode. It should have been done in IM0. 8259 simply slips the opcode
VK> CALL xxxx onto the bus, where xxxx is determined during its programming... The doc is in
VK> Russian, 15 kb zip.

Doc if you can throw it in the soap, but in general it worked for me in IM2, though
not as in the description (I have a description but it’s superficial), it says
(roughly speaking) that the placement of the vector table depends on the word initialization
ICW2, but in practice it turned out that the contents of ICW2 do not affect this in any way,
by scientific poking I found out that in the interrupt confirmation cycle
from 8259 there is always #BF on the bus, regardless of what level the interrupt came, in general, based on this, I assembled dosx now I am testing so far
everything is fine.

Alexandr.

C O M A N D N Y WORDS N I C I A L I S A T I O N (ICW)

Introduction

If a command is issued with A0=0 and D4=1, it
is interpreted as an initialization command word 1 (ICW1).
ICW1 begins the initialization sequence during
which the following automatically occurs:

a. The edge of the sensing circuit is reset, meaning
that after initialization, for an interrupt to occur, the
interrupt request input must transition in the
direction from bottom to top.
b. The interrupt mask register is cleared.
c. Input IR7 is assigned priority 7.
d. The address for slave mode is set to 7.
e. The special mask mode is reset and the status reading
is set to IRR.
f. If IC4=0, then all functions selected in ICW4
are set to zero. (non-buffer mode~, no AutoEOI,
MCS-80/85 system)

NOTE: Master/slave in ICW4 is used only in
buffer mode.

Initialization Command Words 1 and 2 (ICW1 and ICW2):

┌A0─┬D7─┬D6─┬D5─┬D4─┬─D3─┬D2─┬─D1─┬D0─┐
ICW1:│ 0 │A7 │A6 │A5 │ 1 │LTIM│ADI│SNGL│IC4│
└───┴─┬─┴───┴─┬─┴───┴──┬─┴─┬─┴──┬─┴─┬─┘ /0 - not required
│ │ │ │ │ │ ICW4
└───┬───┘ │ │ │└──< 1 - ICW4 required
│ │ │ │ /0 - cascade mode
│ │ │ └──────< 1 - single 8259A
│ │ │ / address interval
│ │ │ / call
│ │ └─────────< 0 - interval 8
│ │ \1 - interval 4
│ │ /0 - response mode
│ │ / by level
│ └──────────────< 1 - reaction mode
│ \ along the front
└────────────────────────────< A7-A5 vector addresses
\ interrupts
\ (only in mode
MCS-80/85)

┌A0┬─D7─┬─D6─┬─D5─┬─D4─┬─D3─┬D2─┬D1┬D0┐
ICW2:│ 1│A15/│A14/│A13/│A12/│A11/│A10│A9│A8│
│ │ /T7│ /T6│ /T5│ /T4│ /T3│ │ │ │
└──┴──┬─┴──┬─┴──┬─┴── ┬─┴──┬─┴─┬─┴─┬┴─┬┘
│ │ │ │ │ │ │ │

│
┌────────────────────── ───────────────────┘
│
│ │A15-A8 interrupt vector addresses
└────┤(in MCS-80/85 mode)
│T7-T3 interrupt vector addresses
└ (in 8086/8088 mode)

A5-A15:
Address of the maintenance routine start page. In
an MCS-80/85 system, eight query levels will
generate accesses to eight cells evenly
distributed in memory. They can be
programmed at intervals of either 4 or 8 memory
locations, therefore 8 routines will occupy a page of 32
or 64 bytes, respectively.
The address format is two bytes long (A0-A15). When
the routine interval is 4 A0-A4, 8259A is automatically
inserted, and A5-A15 are programmed externally.
When the routine interval is 8 A0-A5, 8259A is automatically
inserted, and A6-A15 are programmed externally.
The 8-byte interval is set for compatibility with
existing software, and the 4-byte interval
is best for a compact jump table.
On the iAPX system, the A15-A11 inserts into the most significant
5 bits of the vector byte, and the 8259A sets the least significant
three bits according to the interrupt
level. A10-A5 are ignored, and ADI (address
interval)has no effect on anything.

LTIM:
If LTIM=1, then the 8259A operates in level
interrupt mode. Edge detection logic will be suppressed.

ADI:
Addressed call interval is ADI=1, then interval 4,
ADI=0 interval 8.

SNGL:
Single. Indicates that the 8259A is the only one in
the system. If SNGL=1, ICW3 should not be issued.

IC4:
If this bit is set, ICW4 will be expected. If
ICW4 is not needed, set IC4=0.

Initialization Command Word 3 (ICW3):

ICW3 (master mode)

┌A0┬D7┬D6┬D5┬D4┬D3┬D2┬D1┬D0┐
│ 1│S7│S6│S5│S4│S3│S2│S1│S0│
└──┴┬─┴─┬┴─┬┴─┬┴─┬┴─┬┴─┬┴─┬┘ /1 - connected to the IR input
│ │ │ │ │ │ │ │ / slave 8259A
└───┴──┴──┴──┴──┴──┴──┴┤ 0 - IR input without slave
\ 8259A
\

ICW3 (slave mode)

┌A0┬D7┬D6┬D5┬D4┬D3┬─D2┬─D1┬─D0┐
│ │ │ │ │ │ │ │ │ │ slave identifier
│ │ │ │ │ │ │ │ │ │ ( equal to the corresponding
│ 1│ 0│ 0│ 0│ 0│ 0│ID2│ID1│ID0│ input Master IR
│ │ │ │ │ │ │ │ │ │ 8259A )
│ │ │ │ │ │ │ │ │ │
0 1 2 3 4 5 6 7 ┐
│ │ └─>│ 0 1 0 1 0 1 0 1 │
│ └─────>│ 00 1 1 0 0 1 1 │
└─────────>│ 0 0 0 0 1 1 1 1 │
└ ┘

This word is only read when there are
multiple 8259As in the system and cascading is used, in case
in which SNGL=0. ICW3 will load an 8-bit register whose function
includes

1. In master mode (when either SP=1 or buffer
mode M/S=1 in ICW4), each slave in the 8259A
system is set to "1". During operation, the master issues the first
byte of the call sequence (in the MCS-80/85 system) and, via
cascade lines, allows the corresponding slave
to issue the second and third bytes (in iAPX only the second)
2. In slave mode (when either SP=0 or if BUF=1 and
M/S=1 in ICW4) bits 2-0 identify the slave. The slave
will compare them with the input cascade lines and
when they match, the second and
third (or only the second in iAPX 86) bytes
of the call sequence will be issued on the data bus.

Initialization Command Word 4 (ICW4):

┌A0┬D7┬D6┬D5┬─D4─┬D3─┬D2─┬─D1─┬D0─┐
ICW4:│ 1│ 0│ 0│ 0│SFNM│BUF│M/S│AEOI│мPM│
└──┴──┴──┴──┴─┬──┴─┬─┴─┬─┴/0 MCS-80/85
│ │ │ │ └──< 1 - 8086/8088
│ │ │ │ /0 - normal EOI
│ │ │ └──────< 1 - autoEOI
│ ┌─┴───┴───────────
│ │ 0 X - non-buffer mode
│ │ 1 0 - buffer mode slave
│ │ 1 1 - buffer mode master
│ └────────────────
└───< 0 - no special fully
\ nested mode
\1 - special fully
nested mode

SFNM:
if 1, then special fully
nested mode is programmed.

BUF:
if 1, then buffer mode is programmed. In buffer
mode, SP/EN becomes output and M/S determines
masters and slaves.

M/S:
if M/S=1 is selected in buffer mode, 8259A
is programmed as master, M/S=0 means
slave programming. M/S has no function in
the case of BUF=0.

AEOI:
if 1, program the automatic
interrupt completion mode

mPM:
microprocessor flag: mPM=0 sets 8259A to
MCS-80/85 system operation mode, and mPM=1 to
iAPX mode86.

21 Oct 02 01:10, Alexandr Tkachev wrote to Valerij Kozhevnikoff:

AT> initialization words of ICW2, but in practice it turned out that the contents
AT> ICW2 do not affect this in any way, by scientific poking I found out that
AT> in the interrupt confirmation cycle from 8259 on the bus there is always #BF not

So Kondratiev has the same thing it was. Neither the piss command works nor the Spectrum one. There's a bug somewhere (in smuc) with processing a command request from the
CPU.

VK> Here is a trick. Your 8259 is in 8086 mode (determined by the 0th
VK> bit
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
After studying the docks, I tried all the options for any value
mPM,ICW2,ADI,A5-A7 ICW1 with IM2 the result is the same SD = #BF, with IM0
complete stupor can only be treated with power off, apparently this is the implementation of the
control panel in gusto, which can be seen by digging into the PROM, page 7.

VK> ICW4, and in this mode it needs two INTA pulses, and the vector will be substituted on the
VK> bus only by second.

KF> Kondratiev had the same thing. Neither the writing command works, nor the KF command, nor the Spectrum one. There's a bug somewhere (in smuc) with processing a command request from the
KF> CPU.

Yes, again it's a rake, but you can still work with the control panel, although you'll have to do unnecessary movements.

Alexandr.

KF>> from the CPU.

AT> Yes, again a rake, but you can still work with the control panel, although you will have to make extra movements
AT>.

How is that? I didn’t find any unnecessary movements in your samples. Everything is beautiful, #FF has a clock, keyboard and cursor, #BF has a modem. By the way, open ports rulez. You would borrow a 33600 modem from someone, just to check what the maximum CPS will be.

AT> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
AT> After studying the docks, I tried all the options with any value
AT> mPM,ICW2,ADI,A5-A7 ICW1 with IM2 the result is the same SD = #BF, with IM0 complete
AT> stupor is treated only with power off, Apparently this is the implementation of the control panel in gusto, as
AT> you can be convinced by digging into the PROM, page 7.

Yeah. What if you tear off the 26th leg of the PCP and put a normal INTA there? You can
do it on 1533LL1 or like this:

/M1 ─── |──┬───┬───── /INTA
│ █ 1kOm
/IORQ ─── |──┘ │
─┴─

“mounting OR”
Diodes - KD522.

IMHO, the altera only lets the first INTA through to the control panel, it issues a CALL opcode,
Z80 issues the second INTA and that’s where everything stops. Or is it not? Probably not
so.
Most likely, during development SMUC was jammed into IM0, due to the fact that
frame interrupts cannot be canceled, and with IM0 the handler will always be at
address #0038. It didn’t work out well in IM2, so they made some kind of 8086 emulator, which adds a second one to each INTA from the Z80, so that the vector is output to the bus.
But I don’t understand - why is it always #BF? Look at the diagram, you can see that the 8259 and Z80 data buses are connected only through a buffer on the AP6, which means this #BF comes from it. Where does he get it from?

By the way, even in IM0 you can do it well.You program the watch so that
it generates an interrupt 50 times per second (in SMUC this is IRQ0), for this
interrupt you hang up the keyboard and so on, and for the entire time you work with the modem (when
the INT flag is raised in the SMUC system register) you keep a jar of TRDOS below. She
at #38 has a simple plug from EI:RET. And modem ports are at your fingertips. As soon as
the modem buffer is full, you pause the port, clear the INT flag,
write the buffer to disk, and fill it again...

VK> Laziness. 1.1. it will be without him, a lot has already been done there. I'll do it in 1.2.

More or less settled the subject.
The disk buffer has left 1 sector for now. On floppy computers it will slow down.
A screw or ramdisk is desirable.

What we have now.

1. Works in IS-DOS Chic and classic.

2. Memory supports up to 4 megs (256 pages). Drivers are currently available only up to 1M.

3. Able to download .scr from the screen. The version for 512x192 screen uploads
monochrome unpacked .pcx 512x384. There is a PCX packer, but it glitches on poorly compressed images... So for now without it.

4. In addition, the version for an extended screen can output an image to a
printer (if the driver is installed).

5. Well, Gigascreen is supported.

The typing/saving system can be easily disabled in the source code, so I’ll ask now:
are they needed? Because I feel sorry for the memory...

Now I’ll sit down to finish writing the manual and put everything in the archive. One of these days it will fly into an echo.

The license will be GPL.