fun bug

14 Jan 02 00:05, Vassili Klimov wrote to Ilya Vinogradov:
VK>>>> the hardware does not have time to set to zero the address corresponding to
VK>>>> bit 7 of port 7ffd.
KF>>> It’s unlikely to have time. Most likely, the wire is connected somewhere to another
VK>>> but it’s buggy only on the Ldir command!
IV>> it’s not STS, for an hour, it’s buggy? ;)
VK> nope, first the glitch appeared and only then I got into the STS. By the way, everything
VK> became normal after I replaced ldir with a,(hl):(de),a:inc
VK> de:cpi:jp pe,$-5

There is a glitch somewhere in the software. Are interruptions allowed? Where is the stack?

KF> There is a glitch in the software somewhere. Are interruptions allowed? Where is the stack?
damn, you're teaching an old hacker ;-)) conditions are ideal, if the software was buggy I would
find a bug and wouldn't write here. Apparently the glitch appears due to the fact that
when selecting bank 2, the addresses at the output of kp11 are transferred to the 3rd state and
pulled to the ground by shortcuts and simply do not have time to set to 0.

JTN/4D

VK> damn it, you're teaching an old hacker ;-)) conditions are ideal, if the software
VK> was buggy, I would have found a bug and wouldn't have written here. Apparently the glitch
VK> appears due to the fact that when you select bank 2, the addresses at the output of kp11
VK> are transferred to the 3rd state and are pulled to the ground by shortcuts and simply do not
VK> have time to set to 0.

Unlocking LDIR:

COP 4t., COP 4t., READ 3t., WRITE 5t., (DEC/INC) 5t.

LD A,(HL) : LD (DE),A

COPY 4t., READING 3t., COPY 4t., WRITE 3t.

Maybe he doesn’t have time. There’s no need to do anything with resistors, install a normal
small circuit.
Maybe the memory can also be overclocked to 7Mhz?