CLOCK_!

Sat May 8, 1999 you wrote here:

RM>> #EFF7 bit 7 - enabling access to the clock

KF> Throw it out! Just unnecessary glitches. Since 1998, the clock has been running better

There are no glitches. Let it be.

KF> This is all from ignorance. In 512VI1 leg number 1 is not used or is used - I don’t know.

It’s not documented.

KF> But in Dallas you must connect it to +5 or GND. It sets
the
KF> mode of operation of the microcircuit when choosing a data address (like VI1 or like Dallas).

Well, another addition! :)

KF> And the data sampling time is 200 ms. In turbo mode, you need WAIT
KF> or switch to the standard frequency CLK 3.5 Mhz.

8[ ] With such a time, even at 3.5 WAIT is needed! :)

Here is what is said about this in the document that I have on the 512VI1:
"With a supply voltage of +5V, the write cycle time is at least 1 μs (this includes
the time for setting the address and the time of the actual recording/reading)."
If you believe this, then even in the turbo everything will be OK!
Unfortunately, timing diagrams are not given. :(

And then, if you paid attention, there was a scheme for finalizing the “HD” and
turbochargement of the Penta (and some things there concerned not only the Penta) from AXLR. So,
there it was recommended to extend the /IORQ signal in turbo mode not only
for
VG93, but also for other devices. (For me this extension is not done only for the
controllerscrew.)

All the best.
Sincerely, Roman.

RM> 8[ ] With such a time and at 3.5, WAIT is needed! :)

Error - actually 200 nanoseconds (for Dallas).

Kirill Frolov. [ZX]