CACHE+!

╒═════════ CACHE+! .W ════════════──

CACHE - 62256
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In the Pentagon it is very easy to install CACHE-RAM on 537RU10. V.M.G. published in Spectrofon-17. And not only
for Pentacon.) But with 2K there is little use for it. But 16K is a different matter! It also tells how to make 16K - on two
537RU17 - they need to be soldered “sandwich” on top of each other. But
it is much more convenient to take one bourgeois chip
of static RAM - 62256 (different companies call them differently, I have HM62256LP).
Here a “serious” problem appears - 62256 has
a volume of 32K. Well, let's use 16K as expected. Where the hell should I use the remaining 16K? The idea immediately comes to address them
with bit 4 #7FFD. But all existing cache software was written taking into account the
fact that for any value of this bit we have the same
cache! Sometimes this is necessary! Therefore _you can’t_
just hook the 1st leg to bit 4 #7FFD!
I decided to do this on my computer:

(Fig. 1)
1533KP11
┌──┬────┐ ┌──┬─ +5V
+5V ──────2─┤A0│MX │ │ │
ROM ─────14─┤A1│ │ █ █ All resistors are 1K
┌──11─┤A2│ │ █ █
═╧═ ├──┤ │ │ │
/DOSEN ──────3─┤B0│ Y0├─4─┤ │
с 10н. D66 ──┬──13─┤B1│ Y1├─12───┴── к 1н. 62256
└──10─┤B2│ Y2├─9────┬─███─┐
├──┤ │ │ │ ═╧═
#CFF7 bit1 ──────1─┤S │ │ │ │
#CFF7 /bit4 ────15─╡E0│ │ │ │ ┌──┐ 1533ЛЛ1
└──┴────┘ │ └1─┤1 │
/WR ────────────────────────2─┤ ├─3─ /WR 62256 (27н.)
│ └──┘
│ ┌──┐ 155ЛЛ2
└───2─┤1 │
с 9н. D66 ──1─┤ ├─3─┬─ CS_CACHE
└──┘ │ к 8н. D66
┌────────────────────────────┘
│ КД522 ┌──|<─── +5V
│ ├──|<─── +3V от батарейки
│ ├─────── к 28н. 62256
│ 155ЛЛ2 █
│ ┌──┐ █
└─6─┤1 │ │
/MREQ ──────7─┤ ├─5─┴── к /CS 62256
└──┘ (20н.)

Привязка дана к микросхемам Пентагона! Сигналы:
/DOSEN - 11н. D83 (1н. ПЗУ 27512); ROM - 12н. D62.
Hе забудьте на 26-ую ногу 62256 завести А13 (шина
А0-А15) с Z80, на 2-ую - А12, на 23-ю - А11. (Hа 22-ой
должен быть /RD. А остальные ноги подключаются как и у
ПЗУ.)
28-ая нога -power supply, if it is supplied as indicated, then
the information in the static RAM when the power is turned off will
be stored until the battery runs out. And it consumes
static RAM in storage mode VERY little. (This is exactly why 155LL2 was used!). For non-Pentagon there is one
subtlety. Here is the diagram of V.M.G.:

┌──┐ 1533LL1 (Fig. 2)
A14 ─1─┤1 │
A15 ─2─┤ ├─3──────────────────────────┐
└──┘ 1533TM2 │
A7 ─────────────────┐ ┌─┬──┐ │
/RD ────────┐ │ +5V ─1─┤R│TT├─5────── BLOC_ROM
┌──┐ │ ┌──┐
/OIRQ ─4─┤ ├─6─9─┤ ├─8──────3─┤C│ │ │ ┌──┐
└──┘ └──┘ 10K ├─┤ │ └─13─┤1 │
S1/ +5V ──███──┬─4─┤S│ o─6─┬─12─┤ ├─11─ CS_CACHE
/NMI ─────/ ───────────────┘ └─┴──┘ │ └──┘
TURBO
KD522

Here the last element LL1 must be replaced with an element 155ЛЛ2
and a 1K resistor (LL2 has an open collector output), and
connect its output to the same output of the circuit shown
in Fig. 1. Or you can use the LP8 element here, as in
the Pentagon. and the 13th and 10th legs of KP11 (Fig. 1) must be given a signal from the 6th leg of TM2, to the 1st leg of LL2 (Fig. 1) -feed
from the 3rd leg LL1.

Instead of series 1533 you can put 555.

You can, of course, put a toggle switch on the 1st and 15th legs
KP11 and work with your hands, but it’s better to do this:

bit1 and /bit4 are the bits of the #CFF7 port, obtained like this
in this way:

1533ID7 (Fig.3)
┌──┬────┐
A12 ─1─┤A0│DC ╞─15
A13 ─2─┤A1│ ╞─14
A14 ─3─┤A2│ ╞─13
├──┤ ╞─12
│ │ ╞─11─┐
A3 ─4─╡v1│ ╞─10 │
/OIRQ ─5─╡v2│ ╞─9 │ 1533ЛЭ1 1533ЛЛ1
A15 ─6─┤V3│ ╞─7 │ ┌──┐ ┌──┐
└──┴────┘ └───5┤1 ╞─4──4┤1 │
/WR ────────────────────6┤ │ ┌─5┤ ├─6─┐
└──┘ │ └──┘ │

│ ┌──┬────┐ │
└9─┤C │TT │ 1533TM8 │
RESET ─1─╡R │ │ │
├──┤ │ │
D1 ─4─┤D0│ Q0├─2── bit1 │
│ │ /Q0╞─3 │
D4 ─5─┤D1│ Q1├─7 │
│ │ /Q1╞─6── /bit4 │
D2 ─12┤D2│ Q2├─10─ bit2 │
│ │ /Q2╞─11 │
D0 ─13┤D3│ Q3├─15────────────┘
│ │ /Q3╞─14
└──┴────┘

Who collected GLUK-clocks according to The modified scheme
already has a decoder. (And power to 62256 can be taken
from there.)

Now, if the port is reset,we have a simple CACHE 16K (1st
page 62256). Normal! If you set bit 4 in port
#CFF7, then we have CACHE-32K, where the high address is bit 4 #7FFD.
If you load, for example, TR-DOS
5.04T into a normal CACHE-16K (in my ROM I have TR-DOS 5.12F by REANIMATOR), then
by setting bits 4 and 1 #CFF7, you can use programs critical to the
version of TR-DOS. In this case, you will also have CACHE - the 0th page will be connected!
Bit 0 of port #CFF7, when set, will prohibit programs
from accessing this port until you press RESET (if necessary).

There is another interesting possibility - to connect legs 2
and 11 of KP11 (Fig. 1) like this:

┌──┐1533LA3 (Fig. 4)
/DOSEN ───┤& │
bit2 ─┬─┤ ╞── to 2 n. KP11
#CFF7 │ └──┘
└─────── by 11 n. KP11

Then you can load into the CACHE-32K pages, for example, NeOS
and your version of BASIC-48, set bit 2 #CFF7, and they
will take the place of BASIC-128 and standard BASIC-48.
Writing to them will become impossible.

27 Feb 99 Roman Milukov
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All the best.
Sincerely Roman.