CACHE+

CACHE - 62256.

In the Pentagon it is very easy to install CACHE-RAM on 537RU10.
(The circuit from V.M.G. was published in Spectrofon-17. And not only
for Pentacon.) but with 2K it is of little use. But 16K is a different matter! It also tells how to make 16K - on two
537RU17 - they need to be soldered “sandwich” on top of each other. o
it is much more convenient to take one bourgeois chip
of static RAM - 62256 (different companies call them differently, I have HM62256LP).
This is where a “serious” problem appears - 62256 has
a volume of 32K. at 16K we use it as expected. Where the hell should I use the remaining 16K? The idea immediately comes to address them
with bit 4 #7FFD. All existing cache software was written with
taking into account the fact that for any value of this bit we have the same
cache! Sometimes this is necessary! Therefore _you can’t_
just hook the first leg to bit 4 #7FFD!
I decided to do this on my computer:

1533KP11
┌──┬────┐ ┌──┬─ +5V
/DOSEN ──────2─┤A0│MX │ │ │
from 10n. D66 ───┬─14─┤A1│ │ █ █ All resistors are 1K
└─11─┤A2│ │ █ █
├──┤ │ │ │
+5V ──────3─┤B0│ Y0├─4─┤ │
ROM ─────13─┤B1│ Y1├─12───┴── to 1n. 62256
┌──10─┤B2│ Y2├─9────┬─███─┐
═╧═ ├──┤ │ │ │ ═╧═
#CFF7 bit1 ──────1─┤S │ │ │ │
#CFF7 /bit4 ────15─╡E0│ │ │ │ ┌──┐ 1533ЛЛ1
└──┴────┘ │ └1─┤1 │
/WR ────────────────────────2─┤ ├─3─ /WR 62256 (27н.)
│ └──┘
│ ┌──┐ 155ЛЛ2
└───2─┤1 │
с 9н. D66 ──1─┤ ├─3─┬─ к 8н. D66
└──┘ │
┌────────────────────────────┘
│ КД522 ┌──|<─── +5V
│ ├──|<─── +3V от батарейки
│ ├─────── к 28н. 62256
│ 155ЛЛ2 █
│ ┌──┐ █
└─6─┤1 │ │
/MREQ ──────7─┤ ├─5─┴── к /CS 62256
└──┘ (20н.)

Привязка дана к микросхемам Пентагона. Сигналы:
/DOSEN - 11н. D83 (1н. ПЗУ 27512);
ROM - 12н. D62;
е забудьте на 26-ую ногу 62256 завести А13 (шина
А0-А15) с Z80, на 2-ую - А12, на 23-ю - А11. ( а 20-ой /RD
уже есть...)
28-ая нога - питание, если подавать его как указано, то
информация в стат.ОЗУ при выключеном питании будет
сохраняться пока не сядет батарейка. А потребляет
статическое ОЗУ вstorage mode is VERY small. (This is why 155LL2 was used!).

Instead of series 1533, you can put 555.

You can, of course, put toggle switches on the 1st and 15th legs
KP11 and work with your hands, but it’s better to do this:

bit1 and /bit4 are the bits of the #CFF7 port, obtained like this
in this way:

1533ID7
┌──┬────┐
A12 ─1─┤A0│DC ╞─15
A13 ─2─┤A1│ ╞─14
A14 ─3─┤A2│ ╞─13
├──┤ ╞─12
│ │ ╞─11─┐
A3 ─4─╡v1│ ╞─10 │
/OIRQ ─5─╡v2│ ╞─9 │ 1533ЛЭ1 1533ЛЛ1
A15 ─6─┤V3│ ╞─7 │ ┌──┐ ┌──┐
└──┴────┘ └───5┤1 ╞─4──4┤1 │
/WR ────────────────────6┤ │ ┌─5┤ ├─6─┐
└──┘ │ └──┘ │

│ ┌──┬────┐ │
└9─┤C │TT │ 1533TM8 │
RESET ─1─╡R │ │ │
├──┤ │ │
D1 ─4─┤D0│ Q0├─2── bit1 │
│ │ /Q0╞─3 │
D4 ─5─┤D1│ Q1├─7 │
│ │ /Q1╞─6── /bit4 │
D2 ─12┤D2│ Q2├─10─ bit2 │
│ │ /Q2╞─11 │
D0 ─13┤D3│ Q3├─15────────────┘
│ │ /Q3╞─14
└──┴────┘

Who collected GLUK-clocks according to The modified scheme
already has a decoder. (And power supply for 62256 can be taken
from there.)

Now, ifthe port is reset, we have a simple CACHE 16K (1st
page 62256). normal!

You can load into it, for example, TR-DOS 5.04T (I have TR-DOS 5.12F by REANIMATOR in the ROM), set bit 4
#CFF7, and use programs that are critical to the TR-DOS version. In this case, you will also have CACHE - the 0th page will connect!

Bit 0 of this port, when set, will prohibit programs
from accessing this port until you press RESET (if necessary).

If bits 4 and 1 are set simultaneously, then we have CACHE
32K, where the high address is bit 4 #7FFD.

There is another interesting possibility - to connect legs 3
and 10 KP11 like this:

┌──┐1533LA3
/DOSEN ───┤& │
bit2 ─┬─┤ ╞── to 3n. KP11
#CFF7 │ └──┘
└─────── by 10n. KP11

Then you can load into the CACHE 32K pages, for example, NeOS
and your own version of BASIC-48, set bit 2 #CFF7 and they
will take the place of BASIC-128 and standard BASIC-48.
Writing to them will become impossible. I haven’t done this
yet.

All the best.
Sincerely, Roman.