GLUE-FREE GLITCH SCHEME

3 Nov 98 you spoke here:

KF> Here is, IMHO, the most glitch-free scheme for connecting a clock due to a glitch.
KF> Or rather, there is one signal decoder to which
KF> DALLAS is connected,
KF> port #eff7 - video modes and #cff7 - configuration.

[...there was circuit]

KF> __ __
KF> Glitch-free operation is achieved by using the RD and WR signals at the
KF> final stage of
KF> decoding, which makes the circuit not critical to delays at the
KF> preliminary
KF> decoding stages (within reasonable limits).

KF> P.S. I forgot to add - the clock is not prohibited by bit 7 #еff7.
KF> Because it is
KF> sax and masday.

Well, now your program won’t be able to work for me. What kind of scheme is this
Gluck? More like the FK0 circuit.
:)))
Masdai not masdai, but it is desirable to have additional information protection in CMOS.
There *MAS* hid his watch under TR-DOS...

I haven’t seen the docks on DALLAS.
(And we can’t find DALLAS’s here.)
But in ZXNews-35, it seems, they wrote that this is a complete analogue of 512VI1, only with
battery and quartz. And I saw the document on VI1 very detailed.
So, it has such moments when you cannot access the time cells.
And you ignored this in your time setter for Lara! :-/

We must first look at the UIP flag if it is set to "1"then it goes, or
in less than 244 μs, updating of information in time cells will begin. -
You have to
wait, otherwise you will receive false information. If it is reset, then you have
only 244 µs at your encoder disposal.
(The duration of the time update cycle is 1984 µs with quartz 32.768 kHz.)
The interrupt value should be disabled at any time.
And then it is not necessary to start the /RD signal.
But you can. :)
Or add M1 to ID7.

Good luck.
Roman.