Interrupt controller

Hello, Denis! 26 Nov 98 at 00:29:30, Denis Dmitriev => Valerij Kozhevnikoff: VK>> I have studied Smuk thoroughly. Only small ones remain VK>> ambiguities. VK>> So ask. DD> I remember that an interrupt controller appeared there. How can you force DD> should it work, if at all possible? Two ports in trdos, #7EBE and #7FBE. In the dock at 8259 they are not called in any way, so let them be “even” and "odd". ===================== import file 8259regs.t ================== 3.3.Programming the control panel Below we describe the control panel control in a PC based Intel 8086/8088/80286 microprocessors. Features that allow enable control panels in PCs using other processors are omitted. 2 ports are used to output information to the control panel I/O A port with an even address (usually port 20h) and a port with an odd address (usually 21h). Through these ports there can be 4 initialization words were transferred (Initialization Control Word, ICW1 - ICW4), which set the operating mode of the control panel, and 3 operating control words (work order words, Operation Control Words, OCW1 - OCW3). ICW1 is output to the port with an even address, OCW2 and OCW3. OCW2 differs from OCW3 in that bit 3 in ocw2 is0, and in OCW3 is 1. At the same time, bit 4 in OCW2 and OCW3 is 0, and in ICW1 it is equal to 1. Thus, according to the value output to port c even address, it is clearly determined which register (ICW1, OCW2 or OCW3) data is entered. The odd address port is used to output ICW2, ICW3, ICW4 and OCW1. Ambiguities in the interpretation of data in this case also does not occur, because initialization words ICW2 - ICW4 must directly follow ICW1 brought to the port with even address and output OCW1 in the interval between them follows, it will not be recognized by the controller. Output to a port with an even control word address After initialization of ICW1, initialization of the control panel begins. In progress initialization, the controller sequentially receives controls words ICW1 - ICW4. If there is one ICW3 controller in the system not displayed. The presence of ICW4 is determined by the content of ICW1. When the presence of a cascade of several control panels, each of them is initialized separately. ============================ import end ======================= The INT signal to the processor is usually latched. To unlock, you need to turn on #FFBA bit 3. This is approximately like blocking NMI along A11 in the Kondratiev scheme. Normally #FFBA should contain #77. An inverted clock interrupt signal is supplied to IRQ0, and some leg from altera.Is the alter really generating interrupts? And why? All other IRQ2-IRQ7 are taken from the initial slot. By the way, the int is fed to the Smakov alter through a diode. tikalka Z80 ┌─── 50 Hz SMUC ────┐ │ ┌─── │ │ │ /INT ├────┴─────────|>|────────┤ │ │ It turns out: a moment is possible when tickling and savoring at the same time You really want an interruption. So one of them will be sent to the garden? In the meantime, the program is figuring out who to send, is time ticking? Bad. It would be more correct to shut down the native ticker and force the chat sy tick with a frequency of 50Hz. And the controller has a control word It must be said so that you know who is more important now - the watch or the momed. And here, it looks like the procedure that a shadow person uses to look for a subject. === Cut === ;========================================================================================= LD BC,#FFBA ;interrupt controller detect LD A,(LDFF0) AND #F7 OUT(C),A LD(LDFF0),A LD BC,#7EBE LD A,#F3 OUT(C),A NOP LD B,#7F LD A,#C5 OUT(C),A NOP LD A,#1 OUT(C),A NOP NOP IN A,(C) OR A JR Z,L15A1 CP#1 JR Z,L15A5 L159D LD A,#24 SCF RET L15A1 SET 4,(IY+#1B) L15A5 LD B,#7E LD A,#F2 OUT (C),A NOP LD B,#7F LD A,#C5 OUT (C),A NOP LD A,#FF OUT (C),A NOP NOP IN A,(C) CP #FF JR NZ,L159D SET 4,(IY+#1A) XOR A LD A,#25 RET LDFF0 DEFB #77 === Cut === ============================ import end ======================= WBR, Jason.