Z80 emulation: timing

Hello, boo_boo specifically for the Spectrum? well, perhaps for a tape reader it is important +-40 clock cycles and for port #FF about the same

Hello, All I'm finishing up the z80 emulation, I'm tormented by one question - the timing of write operations memory/port must be strictly observed, the issue is clear... but what about operations reading? that is, I cannot imagine a situation (even an abstract one) in which then at what cycle of instruction execution MREQ+RD[+M1] or IORQ+RD are set does it matter... does it? O__o