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iXBT: Processor classification and naming system Processor classification and naming system Are you yet confused by all these Merced, Katmai, Celeron, Mendocino and others like them? I'm completely confused, that's why made an attempt to classify and sort everything names of x86 processors. To make the article even more informative, wife with the following calculations for each name: family/generation- tion, architecture, clock frequency, system bus frequency, volume first level memory cache, second level cache size, technical manufacturing technology, date of appearance, availability of additional components command hog, physical interface. In any case, the information is up to came from various sources, many of which contradicted to each other. So comments and additions are welcome. Intel Pentium - the very first processors of the P5 family appeared in the distant com March 1993, then Intel, so as not to repeat the mistakes with i486 (the court rejected Intel's claim against AMD regarding the name) decided to give his brainchild a name that later became a household name. Per- The second generation of Pentium was codenamed P5, also known as 80501, voltage power supply 5 volts pin arrangement matrix and was released on clock frequencies of 60 and 66 MHz using 0.80-micron technology, right- yes, it is worth noting that the bus frequency of these processors was equal tocore frequency. They were produced exclusively for Socket 4. The next step in the development of this family was the P54, also known as 80502, supply voltage 3.3 volts pin arrangement checkerboard ritsa, cpuid self-identification instructions have been added to the command set cmpxchg8b and a few more. Appeared exactly a year after P5. When its production already used 0.50, and then 0.35-micron technological process. The clock speed was in the range of 75-200 MHz, and the bus is 50-66 MHz. The volume of the first level cache is 16 KB. Sleep- chals were released for Socket 5, and then for Socket 7. The architecture ra IA32, the command set has not changed since i386. Pentium w/MMX technology - the next big step was the release P55, a processor in which a new set of 57 MMX commands. This happened on January 8, 1997. With the development of technology nology, processors began to be produced using 0.35 micron technology. The supply voltage has changed, decreased to 2.8 volts. corresponding changes in the design of motherboards were required - installation of an additional voltage stabilizer was required. The volume of the first level cache has been doubled - 32 KB. The clock frequency is 166-233 MHz, and the buses are exclusively 66 MHz. Designed for Socket 7. This is the development of the Pentium line for us - desktop computers were discontinued.Tillamook is a processor originally created for use in laptops; thanks to an improved 0.25 micron process su, we managed to simultaneously increase the clock frequency up to 266 MHz, and also reduce core voltage and power. Thus, Mobile computers are on par with desktop computers. He is continuation of the Pentium line and includes 32 KB L1 cache and a set MMX. Produced at clock frequencies from 133 to 266+ MHz with frequency that bus is 60-66 MHz. Packaging type: TCP and MMC. Appeared on January 8 1997. Still in production today. Pentium Pro is the first sixth generation processor. Quite revolutionary revolutionary for its time. In it, for the first time, Intel decided to use second level cache thread, combined in one package with core and operating at processor frequency. Had a very high se- production cost, which has practically not decreased for the entire period of its existence since November 1, 1995. Issued both 0.50 and 0.35 micron technology depending on cache size. The second level cache had a volume of 256, 512, 1024 and 2048 KB. Clock frequency from 150 to 200 MHz. System bus frequency 6-66MHz. Level 1 cache 16KB. Produced exclusively specifically for Socket 8. Pentium Pro supported all pro- Pentium processor (not MMX, of course), as well as a number of new ones in comparisonunderstanding of Pentium instructions (cmov, fcomi, etc.). Double introduced independent tire. Subsequently, all of them were inherited by the Pentium II (in its time, long before its release, Klamath was introduced just like a Pentium II with the addition of MMX).. Significantly ahead your time. Pentium II - P6/6x86 family, first appeared in May 1997. Unites under a common name processors intended for different market segments. Pentium II (Klamath, Deschutes, Katmai, etc.) for the mass market mid-range PC, Celeron (Covington, Mendocino, Dixon, etc.) - for inexpensive low-end computers, Xeon (Xeon, Tanner, Cascades, etc.) for high-performance servers ditch and workstations. Has modifications for Slot 1, Slot 2, Socket 370, as well as mobile versions. Below we Let's look at each family separately. Klamath - the very first Pentium II line processor. Manufactured according to an already outdated 0.35-micron technology, and therefore the clock frequency range is all- th 233-300 MHz. System bus frequency - 66 MHz, cache memory first level - 512 KB, which is located on the processor board and runs at half the processor frequency. Level 1 cache 32 KB. Added MMX block. This is also the first processor for Slot 1. Was released on May 7, 1997. Deschutes - further development of the Pentium II line, improvingadvanced manufacturing technology 0.25 microns. Accordingly but, we managed to raise the clock frequency to 266-450+ MHz, the system frequency dark bus 66-100 MHz, second level cache memory 512 KB located on on the processor board, released January 26, 1998, Slot 1. Per-cache first level 32 KB. Added MMX block. Currently the core Deschutes is used in all processors released today Pentium II line. Tonga is a very interesting processor. His name came across to me first ve in writing this review. The fact is that Intel never did not advertise the fact that the Mobile Pentium II, built on The 0.25 micron core of Deschutes will be called Tonga. True, there is nothing particularly surprising here, it’s just codename, and processors are entering the market under completely different names - mi. In any case, he first appeared on April 2, 1998. So- frequency in the range of 233-300+ MHz, bus - standard 66 MHz. Available as Mini Cartridge Connector and Mobile Module Connector 1 and 2 (MMC-1 and 2). Katmai - Direct descendant of the Deschutes. Changes - the SSE (Streaming SIMD Extensions) block has been added, slightly The set of MMX commands has been expanded, the streaming mechanism has been improved th memory access. Process technology 0.25 microns, clock frequency 450-600 MHz MHz, 512 KB second level cache located onprocessor board Bus frequency 100 MHz, but in September, due to Coppermine delay, 533 and 600 MHz models will be released, calculated at a system bus frequency of 133 MHz. Apparently they will already be done based on 0.18 micron technological process. Celeron is a revolutionary processor in a sense, Intel Somebody paid attention to the mass market of inexpensive computers. In general, this is a whole family of inexpensive processors both with cache second level, and without it. Currently in production or its following representatives are produced: Covington, Mendocino, Dixon. First appeared in April 1998. Available in max for Socket 370, Slot 1. Covington is the first processor in the line Celeron. Built on the Deschutes core and produced in 0.25-micron new technology. Clock frequency 266-300 MHz, system frequency bus 66 MHz, L1 cache - 32 KB (16 KB each for data and instructions) tions), there is no L2 cache. First appeared on April 15, 1998. To reduce cost, it was produced without the cache memory of the second level and protective cartridge. Physical interface Slot 1. Mendocino is a development of the Celeron line. Unlike its predecessor has a second-level cache memory of 128 KB, integrated on the same chip with the core. Clock hour- tota - 300-500 MHz, system bus frequency used today -66 MHz, with plans to move to 100 MHz in early 2000. Techno logical process - 0.25 microns, a transition to 0.18 microns is planned. Due to the fact that the cache operates at the processor frequency, it has very good performance. Released August 8, 1998. First initial form factor - Slot-1, for some time in parallel with the There were Slot-1 and Socket-370 options, today the first one is smooth is supplanted in favor of the latter. Dixon is the next step in the Celeron story. Inexpensive processor in primarily aimed at use in laptops. There will be manufactured using 0.25 micron technology. Cache memory size first level - 32 KB. As in Mendocino, the second level cache is The det is located on the same piece of silicon with the core, but its volume will be increased to 256Kb. Clock frequency - from 300 MHz (Celeron 3090A) and up to 500 MHz, system bus frequency - 66 MHz. Perhaps will be released in Slot 1 version for desktop PCs. Planned for release in the second quarter of 1999. Will contain MMX, but unfortunately without KNI, which Intel will implement only Coppermine - the next non- expensive processor. Coppermine - Pentium III, made on the basis of a 0.18 micron process technology, with 256 KB of L2 cache integrated on the chip. Speed - from 600 MHz and higher. Apparently, along with FSB133 versions, there will be FSB100 variants are also sold (for example, 667/650 MHz). Maxi-The lowest speed expected today is 733 MHz in 2000. Form factor - Slot-1. Possibly the latest Slot-1 processor. Exit dit in November. Coppermine (FC-PGA 370) - a cheap version of Coppermine in form factor FlipChip PGA 370 tore, designed for use with Socket-370 motherboards, and a system bus frequency of 100 MHz. Replacement Pentium II in today's Celeron-Pentium II-Pentium III chain. By the end of this year, the release of 500, 550, and 600 MHz va- riants, at the beginning of the next - 650 MHz processor. Coppermine (FC-PGA418) - Coppermine form factor designed for use with Socket-418 motherboards that provide backward compatible with Socket-370 processors. Server pro- processor oriented for use in dual-processor systems topics. Designed for a system bus frequency of 133 MHz, and speeds from 667 MHz. Release date: first half of 2000. According to the latest information, this option has been cancelled. Coppermine 128K -If you think about the name, then everything becomes much clearer - Mendocino with SSE support. Alleged clock frequency - from 600 MHz, expected release date - 2000 year Timna - Coppermine 128K with integrated on-chip video deocontroller and Direct Rambus DRAM controller. That is, fact- Technically, it’s more of a chipset than a processor. Aimed at superde-cheap PCs and set-top boxes. Estimated clock frequency - from 533 MHz. The estimated release date is 2000. Xeon - after a few years, Intel decided to release a replacement Pentium Pro. Like its predecessor, the cache memory of the second level here operates at the processor frequency. True, if in PPro the cache and the core were combined into one body, then in the Xeon one cartridge. This is the first processor for Slot 2, and is intended for primarily for powerful servers and workstations. Capable work in multiprocessor configurations. Built on the Core Deschutes and is produced, like its own cache, at 0.25 microns technology. By the way, the cache itself has a volume of 512, 1024, 2048 KB, which largely determines the high cost and heat dissipation. Tanner - Pentium III Xeon, that is, it differs from Xeon approximately as well as Katmai from Deschutes. Designed primarily for hi-end servers. Clock frequency from 500 MHz, system frequency - bus 100 MHz, as befits all Xeons CSRAM cache of the second level, operating at a processor frequency of 512, 1024 and 2048 KB. Naturally MMX and SSE, the first level cache is still the same - 32Kb. Intel's first x86 processor, capable of running 8-pro processor configurations. Cascades - Pentium III Xeon based on 0.18 micron technology process. In fact, a server version of Coppermine. On the chipL2 cache 256 KB, clock frequency from 600 MHz, frequency system bus - 133 MHz. Estimated release date is September. Speeds of 800 MHz are planned for mid-2000. Form factor - Slot-2 Willamete - the next fundamentally new IA-32 after Coppermine Intel processor for regular PCs. At least 1 MB L2 cache per chip, a number of steps have been taken to increase production features: added executive modules, decoders, increased large volume of buffers, etc. According to Intel at the same frequency performance will exceed Deshutes and Katmai by 30-50 percent. Production will begin on a 0.18 micron technical process, with post- blowing transition at 0.13 µm. Clock frequency - from 1 GHz and above. Estimated release date: end of 2000, beginning of 2001. Pre- The expected form factor is Socket-423. Foster is a server variant of Willamette. It is possible to build on based on the system bus used in Merced, with the intended bandwidth 3.2 GB/s. Significantly increased cache L1 and L2. Clock frequency from 1 GHz and higher. Estimated date exit - simultaneously with Willamette. Estimated form factor - Slot-M. Apparently the latest IA-32 processor from Intel, a kind of transitional link to IA-64. Merced is the first IA-64 architecture processor, hardware compatiblewith IA-32 architecture, will include a three-level cache memory, including level 0 memory. The performance will be approximately three times higher than Tanner. Manufacturing technology 0.18 microns, clock frequency starting from 800 MHz, system bus frequency - 200 MHz. Also 4 blocks for working with floating point. Will be superior perform Pentium Pro FPU operations 20 (!!!) times. Physical interface: Slot M. Default: MMX, SSE. Planned release date yes - mid-2000. McKinley - scheduled for release in first half of 2001, second generation processor architecture IA-64, clock frequency starting from 1000 MHz. It is assumed that productivity, compared to Merced, will double. A also, the throughput of the data bus will triple, increasing larger (compared to Merced) second-level cache volume and faster grow beyond 1 GHz. As usual, 0.18, and a year later 0.13-micron manufacturing technology. Physical interface - Slot M. Madison - successor to McKinley, planned for release in 2002, in other words, it will be the same McKinley, but built according to medical noah, 0.13 micron technology. Deerfield is a processor expected to be released in 2003. It will be manufactured using Motorola's 0.13 micron copper technology. He is Foster's successor. Like all new processors there will be be released for SlotM. Positioned as an inexpensive IA64 architecture processor operating sneeze stations and mid-level servers. Northwood - IA-64 processor, clock frequency from 3 GHz and higher. The estimated release date is 2003. Form factor - Slot M. AMD K5 is the first AMD processor that was intended for competition with Pentium. And its first processor for Socket 7. Similar to Cyrix 6x86, used PR rating, 75 to 166 MHz. At the same time, using The used system bus frequency ranged from 50 to 66 MHz. Cache L1 24 KB (16 KB for instructions and 8 for data), L2 cache on motherboard, runs at system bus frequency. Creature- There are four versions of the processor: K5-75, 90, 100 (PR-rating according to corresponded to the processor frequency, technological process 0.6 µm). Processor K5-100 (0.35 micron), processors K5-PR120, PR133 (PR rating corresponds to frequencies 90 and 100 MHz, technological process 0.35 µm, recycled core). And processor K5-PR166 (real frequency 66MHz x 1.75) with a non-standard multiplication factor. K6 - began to be delivered in April 1997 (this is Model 6), on me- a month before the release of the Pentium II, produced on the basis of 0.35 microns (later 233 MHz K6 were produced using 0.25 µm pro- process) technological process. The processor operated at a frequency of 166 to 233 MHz. Was created based on the design of the 686 processor, creatinggiven by NexGen, acquired by AMD. Compared to yours predecessor, received an MMX module, increased L1 cache size - up to 64 KB (32 KB each for instructions and data), increased speed The growth of work allowed AMD to abandon the PR rating. In K5 there is solutions were put in place that made it possible to achieve greater productivity activity at the same frequency, namely execution by assumption and internal risk-like organization. All subsequent processes Players from AMD inherited this property. K6 deliveries later began Model 7 (mobile version) with frequencies 266 and 300 MHz, technology ical process 0.25 µm, FSB 66 MHz K6-2 is the next generation of K6. Released in May 98, the main improvements relative to its predecessor began to be support for additional instruction set 3DNow! and system frequencies bus 100 MHz. L1 cache 64 KB (32 KB each for instructions and data), L2 cache is located on the motherboard, and may have volume from 512 KB to 2 MB, operating at system bus frequency. Was released at 266 MHz, today's maximum clock speed frequency is 475 MHz, 500 MHz should be released soon option. There were two models of the K6-2 processor, namely the AMD K6-2 Model 8, operating at frequencies 266 (66*4), 300 (100*3), 333 (95*3.5), 350 (100*3.5) and 366 (66.*5.5) MHz. And the second AMD K6-2 Model9, operating at frequencies of 380, 400, 450 and 475MHz. In K6-2 Model 9 a new core is used, the same as in K6-III, the main difference is in the new kernel (CTX) this is a modified method of working with the cache. Sharptooth (K6-III) is the first processor from AMD to have a second cache th level on the core. Their latest processor, made for the platform mu Socket 7. In fact, it is just a K6-2 with 256 KB of on-chip L2 cache, operating at the same frequency as the pro- tsessor. The L1 cache has a capacity of 64 KB (32 KB each for instructions and data), L3 cache is located on the motherboard, and may have volume from 512 KB to 2 MB, operating at system bus frequency. Was released in February 99 in 400 and 450 MHz variants, preparing Xia to the 500 MHz output option. Argon is the code name for the core used in the K7. K7 (Athlon) - The first AMD project in which it was forced move away from direct copying of Intel architectures, and offer the market create your own version of the platform for PC. The processor has unrivaled for today's x86 processors, the first level cache size is 128 KB (64 KB each for instructions and data). The L2 cache can change from 512 KB to 8 (16?) MB, in the near future to be released Only models with 512 KB of cache operating at 1/3 are planned processor clock speed. System bus - EV-6, same as in Alpha processors, which potentially makes it possible to createmotherboards that support both processors. System speed - The bus is 200 MHz, but has a potential of up to 400 MHz and higher. Support live instruction sets - MMX, extended compared to K6-III 3DNow!. Form factor - Slot A. AMD's first semi- given its own name upon release - Athlon. Available today models 500-550-600-650 MHz. Depending on the size of the L2 cache, the Athlon processors have an additional prefix in the name, for example - Athlon Value, Athlon Ultra and Athlon Select measures. In the second half not a year, an 800 MHz model is possible, presumably at the beginning 2000, with the transition to 0.18 micron process technology and copper technology connections, speeds of 1 GHz will be achieved. Possible in 2000 release of the socket version of Athlon (Socket 370 or Socket 423) K8 - AMD's next project that may produce the same sensation, just like Athlon. The head of AMD says that work on K8 is underway. Jerry Sanders said at Microprocessor Forum'97. However, according to According to AMD representatives, at the end of 98 the processor was still in production. is in its infancy. Very few details are known so far, perhaps but to say only that this will be the first 64-bit processor from AMD - their response to IA-64. It is not surprising that work on the processor led by the creators of Alpha. Will probably use but- The second generation bus for Alpha is EV-7 or EV-8. Like K7, on saleZhu, most likely, will go under a different name. Presumably expected speed - 1.5 GHz and higher, expected release date - second half of 2000 - first half of 2001. Cyrix 6x86 - or M1. To evaluate performance we used PR rating when CPU performance is compared to speed of the Pentium processor at which it would have to run to achieve the same performance. PR rating 6x86 composition- ranged from 120 to 200 MHz. Initial processor options were famous for the presence of errors that led to frequent PC freezes, and the necessary the need for software manufacturers to release patches specifically for this processor. First level cache - 16 KB (single). Hour- The system bus speed is from 50 to 75 MHz. Platform - Socket 7. MediaGX is an offshoot of the Cyrix processor family, the first pro- a processor made according to the PC-on-a-chip ideology. To the 6x86MX core there were memory and PCI controllers were added, video accelerator was integrated into the chip holder, with a frame buffer in the main memory of the PC. In chip-com Pagnon implements a PCI-ISA bridge and integrates sound. PR rating from 180 to 233 MHz, 16 KB L1 cache (single). Produced according to technological process 0.5 microns. Today National makes on the basis of this pro- processor two products - Geode GXLV (0.35 microns, 166-266 MHz) and Geode GX1400 (with added hardware support for MPEG-2, Dolby AC3 andetc). 6x86MX - slightly redesigned for greater performance size 6x86. The L1 cache has quadrupled - up to 64 KB (unit ny), the overall processor performance has increased, added MMX block, support for separate power supply appeared. Used system bus frequency from 60 to 75 MHz. Used PR rating from 166 to 266 MHz. MII - the main Cyrix processor today, began production in March '99. First level cache - 64 KB (single), L2 - as Usually, for Socket 7, it is located on the motherboard, and has volume from 512 KB to 2 MB, operating at system bus frequency. Supported instruction sets are MMX. Uses PR rating. The actual speed in MHz is usually much lower - so, Cyrix MII PR366 has a real speed of 250 MHz. During production the 0.25 micron technical process is used, in the near future it should be re- walk by 0.18 µm. Models with a PR rating are sold today 300-433 MHz. Cayenne is the code name for the kernel used in Gobi and MediaPC. Gobi (MII+) - the processor has two code names at once, which how unusual. At first it was called Jedi, but later, according to to the request of the copyright holder of this title, Lucas Film, was renamed Gobi. The first of the Cyrix processors, designed based on the Socket 370 platform. Supported instruction sets -MMX, 3DNow!. The block of operations with numbers has been significantly redesigned floating point. L1 cache - 64 KB (single), L2 cache - 256 KB on-chip, operating at full processor frequency. It is assumed The processor will be released in November, with a PR rating of 433 MHz. MediaPC - successor to MediaGX, Socket-7 processor, working melting at speeds from 233 to 300 MHz. Same core as Gobi, with added graphics accelerator and peripheral controllers - mi. Status is unclear. Mxi - Socket 7 Pc-on-a-chip, built all on the same Cayenne core, should outperform MediaPC - 333-400 MHz. Status is unclear. Jalapeno is the code name for the kernel used benefits in Mojave. Mojave (M3) - the processor contains 32 KB (16 for data and instructions) L1 cache, and 256 KB of on-chip cache L2. 0.18 micron process technology, significantly improved compared to predecessors of architecture. Supported instruction sets - MMX, 3DNow!. Speed at the time of release - 600-800 MHz (not PR-ray- ting), system bus speed - 100-133 MHz. The chip will have in- integrated memory controller and 3D accelerator. Alleged Release date: second half of 2000. At the moment, in connection with zi with VIA's entry into the microprocessor market and its purchase of Cyrix and Centaur, the fate of the processor is unclear. Rise mP6 is the first processor from Rise, primarily intended forchen for laptops using Socket 7 processors. Corresponding Therefore, it has very low heat generation. L1 cache - 16 KB (8 KB each for data and instructions), L2 - on the motherboard board, from 512 KB to 2 MB, operates at system bus frequency us. An additional MMX instruction set is supported. When assessing ke performance of their processors, Rise, like Cyrix, uses uses PR rating. PR rating from 166 to 366 MHz. In 2000 Rise aims to achieve PR-466-level performance of the mP6. mP6 II is the same, compared to mP6, as K6-III is compared to nia with K6-2. The same core with the addition of 256 KB of L2 cache per chip. SSE support was promised, performance from the PR-200 and above. In August 1999, it was announced that plans to release the pro- cessor, due to its significant increase in price after adding L2 cache per chip. Tiger - mP6 II for the Socket 370 platform. Apparently, the only mP6 II variant to be released. 16 KB L1 cache, 256 KB L2 cache operating at pro-clock speed tsessora. Delivery of samples is scheduled for the end of 1999. Centaur Winchip C6 - the processor was originally created, being oriented bathrooms on cheap PCs, as a result, was inferior in speed to performance to its competitors. System bus 66 MHz,platform - Socket 7. During production, the technical process was used 0.35 µm. The supported instruction set is MMX. Released in October 1997, operated at speeds from 180 to 240 MHz. Winchip-2 - produced using a 0.25 micron technical process. L1 cache 64 KB (32 KB for instructions and data), L2 cache is on the motherboard board, 512 KB - 2 MB. MMX instruction sets supported and 3DNow!. Platform - Socket 7. It differs from Winchip in significantly faster performance the one with floating point numbers. Frequency support now available system bus 100 MHz. Appeared in November 98, speed from 200 to 300 MHz. Winchip-2A - Winchip-2 with a bug fix in the 3DNow implementation. Winchip-3 - 64 KB L1 cache (32 KB each for instructions and data) nykh), L2 cache - 128 KB on chip, operating at processor frequency, L3 cache on- Available on the motherboard, 512 KB-2 MB. Planned for release in the first half of 99, at speeds of 300 MHz and higher. On at the moment, in connection with VIA's entry into the microprocessor market, and its purchase of Cyrix and Centaur, the fate of the processor is unclear. Winchip-4 - Planned for release at the end of 99, at speeds about 400-500 MHz, and when switching to a 0.18 micron technical process - and 500-700 MHz. A change in form factor was expected. At the moment, in connection with VIA's entry into the microprocessor market and its purchaseCyrix and Centaur, the fate of the processor is unclear. August 16, 1999 .@ ╔@╚@@