Elbrus-2000

Hello, All! QUESTIONS AND ANSWERS PRESS CONFERENCE Question: Is the IEEE754 standard implemented in floating arithmetic devices? Answer: Completely implemented, including non-normalized numbers. Question: How many maximum floating point operations can you run in one beat? Answer: In each clock cycle you can run a maximum of 8.5 floating operations comma (the division operation can be run once every two clock cycles, the remaining operations - every beat). Question: Are L1 and L2 caches nonblocking and, if so, then How many misses are allowed before the conveyor stops? Answer: Both caches are non-blocking and allow more than 32 misses, (If, of course, the conveyor does not stop earlier due to the fact that some operation needed the result of the LOAD operation). Question: As you know, the MP ALPHA 21264 abandoned the structure - small, but two-cycle available LI Cache and large comparator, but multi-cycle L2 Cache on chip. Why do you use this structure numerically? Answer: We simulated two variants of the on-chip Cache structure: the first cache with a bit 64 KV with 3 clock access, second - L1 cache 8 KV with 2 clock access plus L2 cache 256KV. with 8 clock cycles available. The simulation results showed that on our In code, the 2nd option gives better results. It should be added that if it allowstechnology, we will increase the size of the L1 cache, leaving the access time to 2 clock cycles. Question: On which models were the characteristics of your microprocessor determined? Answer: We have a multi-level modeling system. All models are docked among themselves. The most detailed, but also, as a result, the slowest is Verilog model, it works at a speed of several commands per second, so it can only be used for small and engineering tests. Next level is an accurate clock-cycle model of the microprocessor, which allows sufficiently large tasks (SPEC benchmarks) to accurately evaluate performance microprocessor. It models all memory levels (caches and memory) and all hardware blocking (i.e. all phases of the hardware pipeline). Finally, the most the fast one is the ISET model. It works at a speed of 2 million wide commands per seconds and allows you to execute almost any user application... Question: Can you do symmetric multiprocessing on your machine? Answer: We binary translate the operating systems themselves, including all OS Microsoft, so they will work as they are written. In our in the architecture, everything is implemented in such a way that if the OS specifically If support for multiprocessing is provided, then it will be provided. Question: Have you already worked with OSes that support multiprocessing?Answer: We translated the Linux 2.0.34 OS kernel through the Elbrus compiler and performed on a model car. Question: Binary translation really looks like a good solution for ensuring compatibility with x86. But why do you think that you will be compatible? with IA-64, since the IA-64 command system has not yet been published? Answer: Someone who has already signed an NDA with Intel probably knows the command system IA-64. We are not. But Merc, as you know, will be compatible with x86 and forced will be compatible with x86 in basic operations and data presentation. In addition, Merced, like us at E2K, uses the approach of explicit command parallelism. Since we are dealing with primitive operations (including memory accesses and floating arithmetic) are compatible with x86, then we are confident that with minor modifications, After IA-64 is published, our processor will also be compatible with IA-64. Question: Don’t you think the productivity loss of 20%-30% with double translation of x86 codes, because many companies, including Intel, spend more power to improve performance by the same 30%? Answer: Indeed, with binary translation, compared to translation with source texts, it is impossible to restore part of the information during analysis binary code. Due to this, losses in productivity occur binary translatable code. But, do not forget that these are losses compared tooptimized similar “native” E2K code. Since our microprocessor will be 3-5 times faster than Merced, even taking into account losses during binary translation we will still be faster than Merced in compatible mode. Question: To achieve the advertised performance, you need to have a compiler for E2k. The compiler, for such an architecture, is very complex, what is it like? reliability level? Answer: We have an optimizing compiler for E2k. We use it for compiling benchmarks and running them on a cycle-by-cycle microprocessor model. Besides In addition, our microprocessor has another unique feature - it provides safe programming. Using this property, E2k can detect there are many more errors in programs than modern ones allow compilers. In particular, we broadcast SPECint92 and SPECint95 benchmarks and found more than 30 errors in them. We use this mode to debug the compiler itself. We broadcast our compiler in the mode ensuring safe programming and then executing it on the model. This allows us to significantly increase the reliability of the compiler. Group of developers compiler has extensive experience, she works on compilers such class for more than 10 years and the current version of the compiler is the third in a row. Question: But this is not enough, how do you test the compiler?Answer: We have established regression testing. We broadcast and perform benchmarks, we have translated and executed OS Linux, we have a test base of 600 MB of various programs in C language and all of them translated and executed in software model of the microprocessor. Best regards, George

Hello All! 0.10 µm 3 GHz Elbrus-2000? - Andy @ 03:47 Boris Babayan, speaking at the HPC Asia 2000 conference, outlined progress Elbrus-2000. This is what the Elbrus company achieved this year. B yours the time when E2K just finished designing, it was oriented at 0.18 microns technical process, in case of delay in financing should have taken place smooth transition to 0.13, and then to 0.10 microns. So, at the conference there were Several E2K options have already been described, optimized for various technical processes: from the slowest (0.18 microns, crystal area 360 sq. mm., dissipated energy - 55 W, clock frequency 1.2 GHz, performance _ 155 SPECint95 and 400 SPECfp95) to the fastest (0.10 µm SOI, 310 sq. mm die area, power dissipation 105 W, clock frequency 3 GHz, performance - 800 SPECint95 and 1150 SPECfp95). Very significant figures for area and heat dissipation owe a lot to the L2 cache, the volume of which in the first model reaches 2 MB, and the second one has 4 MB. Plus, another latest trend of modern microprocessor mode - placement of several processor cores in one case (IBM Power4, Sun UltraSPARC-V, Compaq Alpha 21464) - the new processor can contain up to 4 physical E2K cores. All that remains is to solve a small, but old question - to find a manufacturer.Thanks to Alexey Pylkin (C) 2000, iXBT Hardware, Inc. http://www.hardware.ru http://ixbt.stack.net Best regards, George