Z80/ZX timing questions
ZXNet echo conference «hardware.zx»
Hello icebear
ice> If I'm not lying, you can't turn off the clock in the Z80.
I'm afraid this is not a completely accurate remark. Unlike, say, the 6502, the z80 is entirely
static. Those. shred does not have a minimum frequency, although it is recommended
give short pulses, but as rarely as you like. For example from a button :)
See "The Art of Circuit Design."
Hello, lvd
lvd> No. CALL - one opcode, respectively, and one M1 - at the beginning. A 3 and 4
lvd> next - reading address bytes and decrementing the stack after the last one
lvd> readings. The last 2 to 3 are pushing bytes onto the stack. Compare, for example, with
lvd> PUSH - 5,3,3. The stack is also decremented at the beginning.
Thanks for the clarification, but where does this info come from? I'd like to see it.
In my books there are no details of the M1 cycle for 5 cycles. I *know* that
PUSH - 5,3,3. I just don’t know how exactly. And this is important to me for the correct
testing the screen without WAIT in turbo mode. Can I have a source?
Hello alexfreed
ale> I'm afraid this is not a completely accurate remark. Unlike, say, 6502,
ale> z80 is entirely static. Those. the shred does not have a minimum frequency, although
ale> it is recommended to apply short pulses, but as rarely as desired.
ale> For example, from the button :)
ale> See "The Art of Circuit Design".
I confess, I confused it with the Z180, the clock in it cannot be turned off. By the way, if you're interested,
I can scan a page from the “Microprocessor Kit Z80” regarding the shred.
Hello, boo_boo
boo> 2) commands for working with memory: if with commands that put 1 in memory
boo> byte everything is clear (the byte ends up in RAM after the last clock cycle
boo> command execution), then what about commands that put 2 bytes (PUSH
boo> regpair; EX (SP),regpair; CALL)?
boo> at which clock cycle the first byte appears in memory, and at which -
boo> second? not all at once, the data bus is 8-bit.
In the literature, everything is described with diagrams of signals on the bus.
For example, "Microprocessor kit Z80", Minsk publishing house,
early 90s. Ed. Tsyrulnikov, I don’t remember the author.
Hello Conan
Con> P.S. I think the authors of the booklet do not
Con> sat with oscilloscopes and just processed information from
Con> of the Z80 documentation they obtained. The list of references in the brochure contains
Con> 16 links, most likely the original source is somewhere in them.
The Z80 was well taken apart by the Germans (both Western and Eastern) in the early 80s.
I just don’t understand why we had such a shortage of information if we are with the Eastern
became friends and bought their Robotrons.
Hello alexfreed
ale> In my books there are no details of the M1 cycle for 5 cycles anywhere. I *know*
ale> that PUSH is 5,3,3. I just don’t know how exactly. And this is important for me
ale> correct processing of the screen without WAIT in turbo mode. Can I have a source?
At one time, the question about temporary Z80 tires during PUSH qq also arose among
me. Oddly enough, all brand descriptions available to me at that time were kept
proud silence.
Information was found in the brochure: Minsk
1992 MP . There are cycle diagrams on page 26
NMI confirmations. Since this is an analogue of PUSH PC, the temporary buildings are similar. But
this brochure contained inaccuracies, for example, on page 66 there is a cycle diagram
NMI confirmation contained only 4 clock cycles.
For me at that time (the code for the video processor in ZX-Next was being developed) I needed
there was verified information (both on cycles and on the condition of the tires). Therefore I had to
flash several ROMs and look at real signals with an oscilloscope. This is how they appeared
notes in the margins. However, they practically coincided with the diagram on page 26 (see.
attached figure).
P.S. I think the authors of the booklet did not sit with
oscilloscopes, but merely processed the information they obtainedZ80 documentation. The list of references in the brochure contains 16 references, rather
just the original source is somewhere in them.
File: M1(5).jpg http://zx.pk.ru/attachment.php?attachmentid=2435
Hello icebear
ice> The Z80 was well taken apart by the Germans in the early 80s (both Western and
ice> eastern).
The reference list of the reference book contains book(s) in German.
ice> I just don’t understand why we had such a shortage of information, if with
ice> we were friends with the eastern ones and bought their Robotrons.
Besides the fact that the lack of information (like many other things) was terrible, in the USSR there was no
Z80 were produced. And in the CIS (in Zelenograd and Voronezh) most likely only
Crystals purchased abroad were boiled into cases. At least I don't
received no confirmation that crystals for Z80 processors
were produced somewhere in the CIS.
Hello alexfreed
ale> Thanks for the explanation, where does this info come from? I'd like to take a look.
ale> In my books there are no details of the M1 cycle for 5 cycles anywhere. I *know*
ale> what
ale> PUSH - 5,3,3. I just don’t know how exactly. And this is important for me
ale> correct
ale> testing the screen without WAIT in turbo mode. Can I have a source?
Well, think for yourself. M1 cycle is 4 cycles. It can't lengthen on its own
for example in the regeneration phase for 1 clock cycle? It can't. So bar 5 is simple
added when the processor does nothing with the bus. At this time, SP is decremented,
to push the first byte into the next cycle. Or for example add hl,de -
11 bars altogether? Do you think 7 cycles after M1 percent is doing something shamanic?
tire?...
Hello alexfreed
ale> Thanks for the explanation, where does this info come from? I'd like to take a look.
ale> In my books there are no details of the M1 cycle for 5 cycles anywhere. I *know*
ale> what
ale> PUSH - 5,3,3. I just don’t know how exactly. And this is important for me
ale> correct
ale> testing the screen without WAIT in turbo mode. Can I have a source?
By the way, I found something on the net (I don’t remember where). true with the official
The manual has already found one discrepancy in the duration of M-cycles, though
The official manual is not without glitches anyway...
File: z80ins_Mstates.txt http://zx.pk.ru/attachment.php?attachmentid=2436
Hello, lvd
lvd> M1 cycle - it is 4 cycles. It can’t lengthen on its own, for example
lvd> in the regeneration phase for 1 clock? It can't.
I don't know for sure whether it may or may not. That's why I ask. It seems to me
2 mechanisms possible.
1. 1 Wait state is inserted. There is a precedent - IN/OUT is always added
1 Wait. Why not?
2. The first 4 measures are as always, but between M1 and the next. the cycle is one cycle at all
nothing happens outside.
Once in fact (2), very good. Otherwise the logic analyzer is lazy
connect :)