Would you buy a Z80 20MHz if there was somewhere to install it?
ZXNet echo conference «hardware.zx»
Hello Romanich
Rom> IMHO it is safe to drive CMOS chips, since they have extremely low
Rom> power consumption
For CMOS microcircuits there is an almost linear dependence of the consumed
power versus frequency. Extremely low consumption for CMOS only in static
mode (when there are no switches).
Hello, yoko_ono
yok> since such a mechanism, if it occurs, occurs on any
yok> frequency
This mechanism does not occur at any frequency, but only at frequencies
exceeding the passport parameters for a given series of microcircuits, because this effect
caused by a limited rate of resorption of charges from the parasitic capacitance
shutter, and it is the shutter capacitance that limits the maximum speed
switching field-effect transistors. Moreover, at high frequencies the gate current can
be significant (for example, in switching power supplies in power switches
The gate current can reach several amperes).
Hello Romanich
Rom> Quote:
Rom> Message from Black_Cat
Rom> When the upper key does not have time to close (or vice versa), but the lower one already
Rom> opened, through currents arise from which the crystal heats up so
Rom> it is not possible to touch, although if you notice and cut it off in time
Rom> food, then everything lives. The effect was observed on CMOS RAM.
Rom>
Rom>
Rom> The same thing is observed if the output of the clock generator is direct
Rom> connect with some mikrukhs (V9990,YM2612,...)! Need through
Rom> resistor (units of kilo-ohms) or condenser (tens to hundreds of nanofarads)!
Is the input capacitance large?
Hello pbogdan
pbo> input capacitance is large ?
what was meant by input capacitance? (which I wrote about or which could be
in micros)?
Hello, yoko_ono
yok> In your opinion, does it arise from excess frequency?
Overfrequency may cause through currents due to limited speed
resorption of gate capacitance charges.
dea> This mechanism does not occur at any frequency, but only at frequencies
dea> exceeding the passport parameters for a given series of microcircuits, because
dea> this effect is caused by the limited rate of dissolution of charges from
dea> parasitic gate capacitance
And from the resulting through current, an avalanche-like latch effect is possible,
which can only be eliminated by turning off the power. Why are the spears in vain?
break? Nobody says that this will definitely happen. There they drive CMOS processors in
one and a half times - and it seems like nothing, you just need to keep this in mind when doing serial
using overclocking and it is advisable to have elimination mechanisms for this case
latch effect.
Hello deathsoft
dea> This mechanism does not occur at any frequency, but only at frequencies
dea> exceeding the passport parameters for a given series of microcircuits
dea>
What are you saying? It turns out that the consumption (and heating) of CMOS does not depend linearly
on frequency (minus static current consumption)!
Or perhaps you are talking about the snapping effect (which is what is described in
actually, namely, STRONG heating and it stops only when turned off
food)? In your opinion, does it arise from excess frequency?
Hello, yoko_ono
yok> What are you saying? It turns out that the consumption (and heating) of CMOS is not
yok> depends linearly on frequency (minus static current
yok> consumption)!
yok>
yok> Or perhaps you are talking about the snap effect (which
yok> describes, in fact, STRONG heating and its cessation only
yok> when turning off the power)? In your opinion, it is due to excess frequency
yok> occurs?
To this I can only say one thing: study math. part, physical basis
microelectronics, how field-effect transistors work, what they are
CMOS structures (the dielectric may not be silicon oxide, but
e.g. silicon nitride).
I described the effect associated with through currents, this effect is not observed on
any frequency. And the usual (linear with switching frequency) heating of CMOS circuits
has nothing to do with through currents. When operating CMOS chips on the nameplate
frequency of through currents NO.
Hello fan
"When CMOS microcircuits operate at the rated frequency, there is NO through current."
Gee... This is really funny... :)
Hello, yoko_ono
yok> In the gate (piece of conductor) or in the channel?
There is no need to take the phrase out of context: it was written “rate of resorption
charges from the parasitic gate capacitance" I hope the difference between the gate capacitance and
just the shutter you see. The gate capacitance is formed by a MIS capacitor (about
which is described in any microelectronics course). About p-n junctions in MOS
transistor is generally a discovery (not counting transitions from drain and source to
substrate). There are no p-n junctions there. The gate area is separated by a dielectric (SiO2)
and not a p-n junction as for example in GaAs transistors.
P.S. If you want to continue the debate, it is better to do so in the section
"flame", because The topic raised has nothing to do with the original one.
Hello deathsoft
dea> To this I can only say one thing: study math. part, physical
dea> basics of microelectronics, how field-effect transistors work, what from
dea> represent themselves as CMOS structures (can be used as a dielectric
dea> is not silicon oxide, but, for example, silicon nitride).
dea>
So you better study. Pay special attention to silicon nitride as
dielectric under the gates - since it is so important to you that you
mentioned.
> I described the effect associated with through currents, this effect is observed
> not at any frequency.
>
Well, let's say. Then explain, first, about the resorption of charges where you
you say? In the gate (a piece of conductor) or in the channel?
> But there is no way for normal (linear with switching frequency) heating of CMOS circuits
> is not associated with through currents. When operating CMOS chips on
> there is NO rated frequency of through currents.
Really? Tell this to the CD4000 series microcircuits (supply voltage from 3 to
15 volts) or, for example, Philips, who writes in the datasheets:
┌─- code ───
When the input voltage equals the n-channel transistor
threshold voltage (typ. 0.7 V), the n-channel transistorstarts to conduct and through-current flows, reaching a
maximum at VI = 0.5 VCC for 74HC devices, and
VI = 28%VCC for 74HCT devices, the maximum current
being determined by the geometry of the input transistors.
The through-current is proportional to VCC^n where n is
about 2.2. The supply current for a typical HCMOS input is
shown as a function of input voltage transient in Fig.14.
└── code ───
And he attaches wonderful pictures of the dependence of the through current on the input
voltage.
And finally, you, as an expert in the physical foundations of microelectronics, if you please
explain to us, ignoramuses, how from through currents (MOS transistors in linear mode,
no pn junction is forward biased) latch occurs
(opening of parasitic thyristor structures).
Hello Orionsoft
Ori> and I’m sitting here and realizing that 7 mhz on Scorpio is so not enough for me...
Ori> damn, what should I do?
Make an adapter from Z84@20MHz to Z80C@8MHz ;) and install the first one!
Hello Romanich
Rom> Make an adapter from Z84@20MHz to Z80C@8MHz and install the first one!
If it still worked after that, then everyone would do it :), but until now
So far no one has succeeded.
Hello deathsoft
dea> You should not take the phrase out of context:
dea>
Essentially, you have nothing to say, since you started talking about context?
> it was written "the rate of resorption of charges from the parasitic capacitance
> shutter" I hope the difference between the shutter capacitance and just the shutter you
> you see.
>
Do you see? There cannot be charges in the capacity, just as, for example, there cannot be
be charges in the resistance, since this is a parameter of the circuit (capacitance - ratio
charge to potential - how can it (relationship) have a charge?)
> As for p-n junctions in a MOS transistor, they simply aren’t there (not counting
> transitions from drain and source to substrate).
>
Whether it exists or not, decide! You are a SPECIALIST (supposedly)!
> Article about the thyristor effect and methods of combating it in modern ones
> CMOS chips.
> http://focus.ti.com/lit/an/slya014a/slya014a.pdf
>
> Excerpt from documentation Fairchild Semiconductor (AN-375 1984) about
> thyristor effect for 54HC/74HC series microcircuits;>; "Thanks to some processing refinements, SCR latch-up isn't a problem
> with the MM54HC/74HC Series. There are, however, limitations on the
> currents that the internal metallization and protection diodes can
> handle, so for high-level transients (pulse widths less than 20 ms
> and inputs above VCC or below ground), you must limit the current of
> the ICTs internal diode to 20 mA rms, 100 mA peak. Usually, a simple
> resistor configured in series with the input suffices."
>
I am incredibly glad that you deigned to finally understand the thyristor effect,
We understand what p-n junctions in MOS transistors have to do with it. Please explain
Now how does this effect arise from through current!
> P.S. If you want to continue the debate, it is better to do so in
> section "flame", because the topic raised has nothing to do with the original
> relations.
But it really belongs to the “hardware” section. But, however, continue anywhere.