ULA 4 video modes and all in 64 macrocells

Hello, All Here's an alpha version of the ULA, 64 macrocells in size. which fits neatly into, for example, the Altera EPM7064 MAX This circuit multiplexes 20-bit addresses Supports 4 video modes 1. 256x192 standard 2. 256x192 iron multicolor 3. 512x192 monochrome (with specifics for now) 4. GigaScreen The circuit from KAY-1024 is taken as a basis (I hope I didn’t mutilate it) Features of the 512x192 mode are that the screen attributes are set the same as the last one I read before the switch. nVOE - leg for forming signal blanking The remaining names are taken according to the KAY-1024 scheme (more precisely ANT-1024HD sblive.narod.ru). Attached is a snapshot of the project for Altera Quatrus source in VerilogHDL File: zx_sinhro.rar http://zx.pk.ru/attachment.php?attachmentid=2315

Hello hero her> Here is the alpha version We are going the right way, comrades!!!

Hello Orionsoft What is the most correct duration of the INT signal? at least for KAY and Penatago

Hello caro Please note Taking into account the specifics of the limitation of 64 macrocells, I do INT signal 4 microseconds long all you have to do is go to the counters As for counting M1 signals, unfortunately there is no room

Hello Conan Con> You can make INT half as long when switching to TURBO, but this Con> complicates the circuit design. Maybe I don't understand something, but it seems like this to me: 5-bit counter (1 case) and RS trigger - 1/2 case. The trigger is set according to the CSI and the counter counts the CPU clock. Counted to 32 - RS trigger reset. Very accurately and automatically adjusts to the turbo. No?

Hello alexfreed ale> Maybe I don’t understand something, but it seems like this to me ale> Very accurately and automatically adjusts to the turbo. No? Yes. Everything is exactly as you said. A pair (three) of small bodies is added logic. P.S. Now this complication looks insignificant, in the late 80s early 90s it would cost 10 rubles (with a salary of 150). If recalculated to modern relationships, it will become clear why the simplest models () were so popular.

Hello alexfreed ale> 5-bit counter (1 case) and RS trigger - 1/2 case. Total 5 macrocells and I want (64 in total that would be 63 takes up everything else) In addition, the mikruhi anal LVTTL costs $1.5 dollars Here, if you move further to a family that is larger in capacity, there will be a lot left space is empty, there are not enough pins to realize something cultural inside mikruhi, I already disabled JTAG in this project to create 4 more legs MAX 3064 does not have this crap, so by default there are 4 legs available more to the user

Hello hero her> 64 in total 63 takes up the rest I really don’t recommend trying to use 100% of the resources. Should always be a small reserve because almost always you have to change something slightly. her> implement something cultural inside there are not enough pins for mikruhi It looks like we will have 2 different options. I'm pretty full right now XC95108. Fortunately, she has 84 legs, so her legs are fine. Inside is done and video, and MMU. On the outside there is almost nothing left for petty logic.

Hello alexfreed ale> Fortunately, she has 84 legs, so her legs are fine The max7064 also has 84, but you can’t use everything, at least because the power supply is there need to poke ale> It looks like we will have 2 different options. I'm pretty tight right now ale> filled with XC95108. What's the difference between the description and here it looks like no problem, you just need the source code write at least so that both synthesizers can understand it. ale> I really don’t recommend trying to use 100% of resources About 45 triggers are used (and according to Alter, accordingly macrocells), the rest are occupied by tracing and logic, so there is where they'll go wild, but there's nowhere to put the triggers :)

Hello hero And regarding the minimum number of cases, you can, for example, take the ciclone II from the alter there the percentages fit at a frequency of about 40 MHz and everything else is according to the price list at altera.ru costs 16 dolors plus a mikruha configuration ROM of 3 dolors and will be the whole spec together in VG93 in one mikruha, also there and atemgu or another you can plug in a microcontroller and all the bells and whistles (everyone’s dreamed sprite engines, moving memory blocks, etc.), but most mikrukh have 144 paws without a soldering iron the stations are not soldered so I don’t consider this initially and the board will be the size of the sockets stuck on it

Hello hero her> And regarding the minimum of buildings, you can take, for example, from alter her> ciclone II I've already done this. True, not spec, but Apple and BK0010. And on a ready-made board for $99. It will be necessary to make firmware for the spec on it.

Hello hero her> The max7064 also has 84, but you can’t use everything, at least because her> you need to put food there Well then, I don’t know where you’re putting your feet. There are 69 of them left on i/o. module zx2_dram(clk14,reset,R,G,B,bright,sync,ioreq,memreq,refr,wr_n,rd_n,M1, ram_addr_m,ram_data,cpu_data,cpu_addr,cas_n,ras_n, A14_rom); Macrocells Product Terms Registers Pins Function Block Used Used Used Inputs Used 102/108 (94%) 273/540 (51%) 65/108 (60%) 56/69 (81%) 201/216 (93%) That is 13 more legs left.

Hello hero ld b,b and the like are not allowed - almost any tape or tr-dos protection is full them

Hello, CHRV CHR> commands by writing one to which thread port I agree it should be included since it’s a rather non-trivial extension, but very functional

Hello alexfreed Here's a mental breakdown I was wondering what team the Z80 was missing here? And then I came up with something missing catastrophically commands for intersegment transition, and then I thought, is it possible without It turns out that it’s possible to change the processor crystal using slow protons :) only the ULA needs to be completed. The essence of the idea is to use very smart team LD B,B. It is thanks to her amazing intellectual properties, the impossible becomes reality. It will work like this The intersegment jump command JP 34:FC00 in the assembler interpretation will be look like this LD B,B DB #34 JP #FC00 Tempting? Especially if you consider the option of adjusting the translator. A ULA will take the following steps 1. LD B, B yeah, intersegment transition command, well, let’s feed it to the processor 2. DB #34 this is the page we are interested in, let’s remember it and feed it to the processor NOP command 3. JP #FC00 and we will also feed this command to the processor 4. Now we wait for cycle M1 and when it starts, we change the page to the remembered one Simple? Then I thought the transition was good, but somehow it doesn’t work out algorithmically, I have to would call the subroutine and return CALL 34:FC00 and RETF we will call on the great and mighty teams LD C, C and LD for help D,D So let's look at the command CALL 34:FC00, we will interpret this matter yes LD C,C DB #34 CALL #FC00 Let's look at what ULA will do1. LD C, C yeah, intersegment transition command, let’s feed it 2. DB #34 remember the page number and feed the processor the PUSH HL command 3. The processor, unsuspectingly, executes the PUSH HL command and we are at this moment We meanly disconnect it from the data bus and set it there one by one #0034 :) 4. CALL #FC00 feed it to the processor 5. Wait for cycle M1 and change the page number when it arrives The most vile RET command remains; during its execution you will have to die disable all types of interrupts. LD D,D POP HL RET 1. LD D, D yeah intersegment return command, feed it 2. POP HL we will feed this team too 3. While executing this command, we will remember the lower half of what we read word bus somewhere inside the ULA 4. RET feed it to the processor 5. Wait for cycle M1 and change the page number That's it. But there is one thing in every procedure that has the FAR type (tobish called by the intersegment subroutine call command), must have a header which swaps two words at the top of the stack (this is for the command to work long return), but I think you can pay for such extensibility software and can actually call procedures within 4MB, why 4? But because the most significant two bits of the address are always set to 1 and actually do not participate in addressing, we get (8+14)^2 =4Mb. Why the elders two bits are 1, but because the window for projecting additional memory is locatedat addresses #C000-#FFFF and have the common property of the two most significant bits such as mentioned above Verdict? PS You can consider two more commands: switching the page LD E,E DB #34 and switching the page during the execution of one command LD H,H #34 peculiar segment replacement prefix. And let's call another LD (HL), (HL) HALT and let it stop the processor :)

Hello SMT SMT> ld b,b and the like are not allowed - almost any tape or tr-dos SMT> protection is full of them Well, nothing prevents you from activating the LD r,r command mode by writing a 1 in which thread port. Disabled by default. I repeat, the idea is not new (in Sprinter it is used) and is quite convenient.