Spectrum RAM, RU5 chip

Hello, All I'm interested in this thing: take a standard zx-spectrum or its clones, it has costs 48kB of RAM, more precisely 64kB, but only 48 are used. For hardware - it costs 8 RU5 microcircuits. One RU5 according to the documentation is 256x1 bits (8 address bits), and since here there are 8 of them connected (the addresses are connected in parallel, and each bit of the chip is one from data bits), then in theory 256 bytes can be addressed. Where does the whole thing come from? 64kB? This is if RU5 were 256x2 bits, then it would be just 64kB, but we have 1 bit. Here I have enclosed a clipping from Leningrad of the first "sheme.rar" Documentation on RU5... for example: http://www.inp.nsk.su/~kozak/ttl/ttlh133.htm What's the clue? Please explain, I can’t understand. I read a lot of docs but didn't find anything. And also... what is memory regeneration? :smile; File:; sheme.rar http://zx.pk.ru/attachment.php?attachmentid=4730

Hello, Sap Sap> (8 address bits) 8 bit row address and 8 bit column address, and 16 bit address (/CAS and /RAS are used to latch halves of an address).

Hello deathsoft Why then do they write everywhere in the documentation that physicists can only save 256 bit?

Hello, Sap The> 565ru6 - 16kbit The> 565ru5 - 64kbit The> 565ru7 - 256kbit The> all chips are dynamic memory, organized in the form of an NxN matrix. May I add?: 565ru6 - 16 kbit - 7x7 - 8 mskh = 16 kbyte 565ru5 - 64 kbit - 8x8 - 8 mskh = 64 kbyte 565ru7 - 256 kbit - 9x9 - 8 mskh = 256 kbyte

Hello, Mikka_A 565ru6 - 16kbit 565ru5 - 64kbit 565ru7 - 256kbit all microcircuits are dynamic memory, organized in the form of an NxN matrix.

Hello, Sap Sap> ...........Documentation on RU5... for example: Sap> http://www.inp.nsk.su/~kozak/ttl/ttlh133.htm Sap> Which chip did you look at? Did you even look at it yourself? this is not 565RU5 1x 64K (upD4164C-12) that's what RU5 is