SMUC unknown ports

Press RESET immediately, All! Below is the breakdown of SMUC ports. Questions indicate ports unknown purpose. The A9 signal is not output to the ISA bus, which also seems strange. It would be nice if anyone having a real piece of hardware clarified the conditions for sampling the controller (IMHO I’m there added extra signals) and the purpose of unidentified registers. There are questions: when accessing which ports, reading and writing occurs in IDE drive registers -- when accessing the shadow register containing the most significant 8 bits of the data bus drive, or when accessing the low part of the data register? What serial EEPROM chip (connected via I2C, small like this, 8-pins) installed in the SMUC controller? 256 bytes or more? Yes guess what's inside The same thing is written that is written to the 15th sector of the tr-dos disk. That is Autoloading can be done not only from the disk, but directly from the eeprom. Where is the alarm output (interrupt, that is) of the RTC chip (512VI1) connected? aka "CMOS")? On IRQ0 of the interrupt controller? Where are IRQ1,2,3 connected to? Have they been taken out somewhere? interrupts (IRQ2-IRQ7) from the ISA slot? Must go to PIC (controller interrupts type 580VH59). CONTROLLER SELECTION CONDITIONS: { a0=0 } AND { a1,a5,a7,a11,a12=1 } AND {trdos active} | | ! ISA-BUS ADDRESSES: | ! a8,a9,a10,a13,a14,a3,a4 isa/ide/pic address (A0-A6)| | +- a6=1 access to ISA slot | | (!) INFLUENCE OF A13 ON THESE PORTS IS UNKNOWN! | | | +- a2=1 | | | | | | | | +- a15=1 ??? (ISA A9 ?) UNKNOWN REGISTER | | | | | | | +- a13=1 ??? | | | | | | | +- a13=0 ??? | | | | | | | | +- a15=0 isa bus ports rw | | | isa address bits(A9-A0): (cp==control port bit) | | | { ? (0), cp.2, cp.1, a4, a3, a14, a13, a10, a9, a8 } | | | | | +- a13=1 ??? | | | | | +- a13=0 ??? | | | | | +- a2=0 ??? | | | +- a15=1 ??? UNKNOWN REGISTERS | | | | | +- a13=1 ??? | | | | | +- a13=1 ??? | | | +- a15=0 ??? | | | +- a13=1 ??? | | | +- a13=0 ??? | | +- a6=0 access to SMUC devices | | +- a2=1 access to IDE and PIC controllers | | | | | +- a15=1 ide controller ports | | | | | +- a13=1 ide interface registers rw | | | | | +- a13=0 shadow ide register rw ? | | | | | +- a15=0 interrupt controller register block rw | | | +- a13=1 | | (what is the impact of this bit) | | (for operation of SMUC and controller) | +- a13=0 (interrupts? unknown) | | +- a2=0 | | +- a15=1 rtc/control port | | | +- a13=1 control port | | + bit0 isa/pic/ide reset (0 active) wo | | + bit1 A7 ISA wo | | + bit2 A8 ISA wo | | + bit3 enable interrupts from pic (1 active) wo | | + bit4 SDA out wo | | + bit5 write protect NVRAM (1 active) wo | | + bit6 write SCL, read SDA rw | | + bit7 0=(rtc read, ide command register block), | | 1=(rtc write, ide status register block) wo | | | +- a13=0 rtc port | control port bit7=0 write address, read data | control port bit7=1 write data | | +- a15=0 fdd status port rw + bit7 1=drive A: real disk, 0=emulated + bit6 1=drive B: real disk, 0=emulated ro = read only rw = read and write ps: I have a port plate from Jason...

Greetings, Kirill! On Wednesday July 17, 2002 at 21:27:32 Kirill Frolov and All talked about SMUC unknown ports. KF> The A9 signal is not output to the ISA bus, which also seems strange. It would be According to the IBM specification, the A9 line for "external" IBM PC XT devices should be able to log. 1, this is provided in hardware in SMUC. KF> Which serial EEPROM chip (connected via I2C, KF> such a small one, 8-pins) installed in the SMUC controller? Volume 256 KF> byte or more? There is an assumption that the same thing is written inside: KF> is written to sector 15 of the tr-dos disk. That is, autoloading can be done without KF> only from the disk, but directly from the eeprom. All HDD parameter settings and other variables used by the Shadow Service Monitor, and user-assigned, are stored in the non-volatile IC memory (NVRAM)-24LC16B with a capacity of 2Kb. All these settings are read from NVRAM when turning on the power, as well as when fully initializing RESET + CS/5. KF> Where is the alarm output (interrupt, that is) of the RTC chip connected KF> (512VI1 aka "CMOS")? KF> On IRQ0 of the interrupt controller? Where are IRQ1,2,3 connected?IRQ0 - CMOS; IRQ1 - HDD; IRQ2-7 - IBM XT slot. KF> Are they displayed somewhere KF> interrupts (IRQ2-IRQ7) from the ISA slot? Must go to PIC (controller KF> interrupts type 580VH59). Yes, that's where they go. All the best, Kirill! Best wishes *** Sergey ***! >>

Press RESET immediately, Sergey! 20 Jul 02 19:02, Sergey Cherbynin wrote to Kirill Frolov: KF>> The A9 signal is not output to the ISA bus, which also seems strange. It was KF>> would be SC> According to the IBM specification, the A9 line for "external" IBM PC XT devices should SC> be able to log. 1, this is provided in hardware in SMUC. For example, the hard drive is connected to ports 0x170-0x17f and 0x370-0x37f. And signal A9 just selects a block of registers. And the screw controller happens on a multicard (or on a sound card, address 0x168), that is, an external one is obtained. KF>> Where is the alarm output (interrupt, that is) of the microcircuit connected KF>> RTC (512VI1 aka "CMOS")? On IRQ0 of the interrupt controller? And where to KF>> are IRQ1,2,3 connected? SC> IRQ0 - CMOS; IRQ1 - HDD; IRQ2-7 - IBM XT slot. Does SMUC have HDD interrupts? At least something was not done per anus. Only the 8-bit ISA connector has 6 interrupt requests, and the 580BH59 only has 4 entries! Something doesn't work out as you wrote. And there is also a question: in new versions (1.3 it seems) of SMUC something is not observed neither interrupt controller, no socket for it. Where are the interrupts connected?

Hello, Kirill! Sunday July 21, 2002 at 01:55:38, Kirill Frolov => Sergey Cherbynin: KF> Press RESET immediately, Sergey! KF> 20 Jul 02 19:02, Sergey Cherbynin wrote to Kirill Frolov: KF>>> The A9 signal is not output to the ISA bus, which also seems strange. It was KF>>> would be SC>> According to the IBM specification, the A9 line for "external" IBM PC XT devices should SC>> be able to log. 1, this is provided in hardware in SMUC. A9 = +5v KF>>> Where is the alarm output (interrupt, that is) of the microcircuit connected SC>> IRQ0 - CMOS; IRQ1 - HDD; IRQ2-7 - IBM XT slot. KF> Does SMUC have HDD interrupts? At least something was not done per anus. KF> Only the 8-bit ISA connector has 6 interrupt requests, and the 580BH59 KF> only 4 inputs! KF> Something doesn’t work as you wrote. 1810BH59A eight inputs KF> And there is also a question: in new versions (1.3, like) of SMUC something is wrong KF> neither observed KF> interrupt controller, no socket for it. Where are they connected? KF> interrupts?I have 1.3, I didn’t have the controller itself, the panel for it was initially located next to it with CMOS. Alexandr.