smuc

Hello, Aleksandr! 01 Nov 02 18:51, Aleksandr Majorov -> Valerij Kozhevnikoff: AM>>> And, IMHO, you’ll end up with 50...100 small chips - you’ll go nuts AM>>> collect :) VK>> Look at the diagram. And think with your head. Where are there 50 chips from? Out of 100 VK>> I’ll collect the second Spec for you. Alternative can be emulated at ~5-10 VK>> small logic packages. Are the ports known? Known. What are they VK>> decryption is the tenth thing. AM> Uh-uh, can you prove your words? AM> I doubt that 10 packages of _fine_ logic will be enough for at least AM> IDE controller of the screw. So I’m getting 10 pieces of 155LA3, let’s get the diagrams AM> collect :-)) 11 buildings. Two IR23, one TM9 and loose powder. Get the diagram from ZXNext here http://www.fortunecity.com/skyscraper/mousepad/767/hardware/hdd/hddshema.zip and mix up the addresses on the decoder so that you get the same ones. The Next scheme is a little suboptimal, since in the original it is on one board it also houses the XT keyboard and 512 memory controllers (by the way, all together that's 17 chips in total), and some things can be simplified to fit into 10 chips. It works with all screws, unlike the Nemov one with 6 chips.PS: MAS, it’s good to play the fool. You know yourself what is possible. ;) You're famous online the fact that he is ready to go out of his way to do nothing. And the rest for this you're knocking. WBR, Jason. /*e-mail: jason2000(scary dog)yandex.ru ICQ: 62235830*/ /np:/ *Aria - Paradise Lost* [paused]

Hi all. If anyone has a diagram of the SMUC controller and a description of the ports, maybe can you share? Thanks in advance. Bye.

Press RESET immediately, Dimka! 12 Nov 02 08:47, Dimka Zaycev wrote to all: DZ> If anyone has a diagram of the SMUC controller and a description of the ports, DZ> maybe you can share? At Kozhevnikov's... I can send it by email. And the ports are: Below is the breakdown of SMUC ports. Questions indicate ports unknown purpose. The A9 signal is not output to the ISA bus, which also seems strange. It would be nice if anyone having a real piece of hardware clarified the conditions for sampling the controller (IMHO I’m there added extra signals) and the purpose of unidentified registers. There are questions: when accessing which ports, reading and writing occurs in IDE drive registers -- when accessing the shadow register containing the most significant 8 bits of the data bus drive, or when accessing the low part of the data register? What serial EEPROM chip (connected via I2C, small like this, 8-pins) installed in the SMUC controller? 256 bytes or more? Yes guess what's inside The same thing is written that is written to the 15th sector of the tr-dos disk. That is Autoloading can be done not only from the disk, but directly from the eeprom. Where is the alarm output (interrupt, that is) of the RTC chip (512VI1) connected? aka "CMOS")? On IRQ0 of the interrupt controller? Where are IRQ1,2,3 connected to? Have they been taken out somewhere?interrupts (IRQ2-IRQ7) from the ISA slot? Must go to PIC (controller interrupts type 580VH59). CONTROLLER SELECTION CONDITIONS: { a0=0 } AND { a1,a5,a7,a11,a12=1 } AND {trdos active} | | ! ISA-BUS ADDRESSES: | ! a8,a9,a10,a13,a14,a3,a4 isa/ide/pic address (A0-A6) | | +- a6=1 access to ISA slot | | (!) INFLUENCE OF A13 ON THESE PORTS IS UNKNOWN! | | | +- a2=1 | | | | | | | | +- a15=1 ??? (ISA A9 ?) UNKNOWN REGISTER | | | | | | | +- a13=1 ??? | | | | | | | +- a13=0 ??? | | | | | | | | +- a15=0 isa bus ports rw | | | isa address bits(A9-A0): (cp==control port bit) | | | { ? (0), cp.2, cp.1, a4, a3, a14, a13, a10, a9, a8 } | | | | | +- a13=1 ??? | | | | | +- a13=0 ??? | | | | | +- a2=0 ??? | | | +- a15=1 ??? UNKNOWN REGISTERS | | | | | +- a13=1 ??? | | | | | +- a13=1 ??? | | | +- a15=0 ??? | | | +- a13=1 ??? | | | +- a13=0 ??? | | +- a6=0 access to SMUC devices | | +- a2=1 access to IDE and PIC controllers | | | | | +- a15=1 ide controller ports | | || | +- a13=1 ide interface registers rw | | | | | +- a13=0 shadow ide register rw ? | | | | | +- a15=0 interrupt controller register block rw | | | +- a13=1 | | (what is the impact of this bit) | | (for operation of SMUC and controller) | +- a13=0 (interrupts? unknown) | | +- a2=0 | | +- a15=1 rtc/control port | | | +- a13=1 control port | | + bit0 isa/pic/ide reset (0 active) wo | | + bit1 A7 ISA wo | | + bit2 A8 ISA wo | | + bit3 enable interrupts from pic (1 active) wo | | + bit4 SDA out wo | | + bit5 write protect NVRAM (1 active) wo | | + bit6 write SCL, read SDA rw | | + bit7 0=(rtc read, ide command register block), | | 1=(rtc write, ide status register block) wo | | | +- a13=0 rtc port | control port bit7=0 write address, read data | control port bit7=1 write data | | +- a15=0 fdd status port rw + bit7 1=drive A: real disk, 0=emulated + bit6 1=drive B: real disk, 0=emulated ro = read onlyrw = read and write ps: I have a port plate from Jason...

Press RESET immediately, Alexander! 13 Nov 02 10:27, Alexander Shushkov wrote to Kirill Frolov: KF>> In Nemovskaya this is corrected by resoldering 4 wires. KF>> No details needed. AS> Guys, tell me what needs to be corrected in the Nemov scheme, otherwise it’s not in the course AS> I. Read this echo... 2All: Who has the largest database of HARDWARE.ZX and CODE.ZX? I only have ~1500 letters. That is, since June 17, 2001. And what was before that was lost. :-( = Hardware on the Spectrum (500:812/1.507) ========================== HARDWARE.ZX = Msg : 346 of 417 Snt Loc Scn From : Kirill Frolov 500:812/1.507 22 Mar 01 00:57:36 To : All 22 Mar 01 00:57:36 Subj: WHO DOESN'T WORK WITH NEMOV'S CONTROLLER? WHO DID NOT WORK FOR? =================================================================================== Press RESET immediately, All! If there are such people or if it didn’t work for someone, and then after any shamanism has earned, please test my bugfix. He helped me. Screw conner on 210mb. Without bugfix, the driver hung, and the screw light blinked. But I can't check mine controller on different models of hard drive problems. The reasons for the problems I see are thatchip type ID7 (series is not important) has outputs that are not very well suited for operation for a long time the hard drive loop and, as a result, a cycle of writing to registers at least bifurcates, and the screw command entries and the driver become out of sync, the driver hangs forever polling cycle... There is also a second potential bug of the scheme that I have not identified: when writing a word to hard drive The data in the drive is captured on the positive edge of the IOWR signal. A register IR22 which stores the contents of the higher half of the address bus and is also controlled by the IOWR signal. If the hard drive reacts to changes in the IOWR signal longer than the IR22 register turns off (plus signal delay in the loop), then an erroneous value will be written to the high byte of the word. All bugs can (should!) be fixed with this bugfix: 1. Return the circuit to its original form (so that everything is like Hemo’s, otherwise it won’t have meaning). 2. Doesn't work? This is very good! 3. RESET is applied to the screw directly, bypassing the AP5 chip. 4. Instead of RESET, pass through the AP5 chip (to the same contacts) the IOWR signal directly from the ID7 decoder and only then goes to the rest parts of the diagram. 5. Signals HA2 and IORD passing through AP5 change places. That is, HA2 must in As a result, go through the AP5 half controlled by the EBL signal, and IORD through constantly included half. 6. Turn on, test...7. TESTING DISK WRITES ON LARGE FILES, counting CRC, not checking Were you beaten? It’s better to do it in iS-DOS on a partition of the hard drive that you don’t mind accidentally ruin it! 8. We write the report in the echo, in the soap... 9. For greater reliability (and even more so if there were problems in point 7) OE chip input IR22 (the one that is connected by outputs to the higher half of the data bus screw) instead of IORW An INVERTED IORD signal is supplied. That is, it will be necessary to pay put 1533ЛH1 or something similar. 10. VS█. P.S.: There is also a very easy way to increase the data reading speed from the hard drive to 125% of the current value - instead of A0, use the second decoder A8. Now reading (the original Nemov circuit) occurs like this: INC C INI DEC C INI .... And it will happen like this: INI INI .... The recording speed does not change during modification. It is worth remembering that on average read usually many times more than written - fast reading is much more important slow recording. Refinement does not make sense on cars with turbo mode - speed increase will be scanty. -+- [ZX] + Origin: Registered Linux User #204355 (500:812/1.507)

Hello, Alexandr! 15 Nov 02 03:13, Alexandr Tkachev -> Valerij Kozhevnikoff: VK>> Exactly... So this #BF is the only possible vector. In IM0 VK>> you can’t work (CP A doesn’t do anything worthwhile). AT> It's a pity that this is so, and not humanly, if from several devices AT> interruptions need to be processed... you'll have to poll the control panel once again AT> for identification. It's okay. By the way, have you tried level interruption? IMHO, if according to the level - noise immunity will be higher. Or it won't work at all. AT>>> INTA I soldered the same song, I think that the control panel is all that comes from it AT>>> required does, but does this fall into the bus question. VK>> There is simply nothing else left. That's all true. We need to complete the document. A VK>> your DOSX can probably already be released to the people. AT> The bug is there, I told you... for some reason I discovered the reason through AT> some time after starting the transfer (namely a large file) AT> unmasked IMR result infinite loop That is? Are there zeros there? So what?AT> has to be written there every time after processing the next interrupt AT> %11101111. Hmm... Why is that?.. I see four reasons: 1. You are up to something with ICW or OCW. OCW2 or OCW3, most likely. EOI specific? Special mode Do you use masks (SMM)? There are modes shift/rotation of anything, priorities and masks can dynamically change... In general, throw the sorets into the echo, we’ll see, we’ll think about it. Try to specify ALL ICW/OCW unambiguously when initializing, so that there were no ambiguities. 2. Somewhere there is an appeal to a shadow person, and he adds all sorts of bad bytes to the control panel writes down why he forgets what and how to do. What screw driver? Clock What are you asking through? Is RST 8 used anywhere? 3. Specifically, your copy of the PKP is buggy. Borrow a thread from someone and try it with him. 4. I just thought of it. Try placing a stub in the Sio_Open procedure. So that the control panel is initialized ONCE - at the start of the Wild. Something like: M1 JP M2 M2 LD HL,END LD (M1+1),HL ... ... END POP HL,BC RET PS: Do you have a printer? I advise you to print out the document and study the paper version. Rulez, when everything is before your eyes. WBR, Jason. /*e-mail: jason2000(scary dog)yandex.ru ICQ: 62235830*/ /np:/ *silence*

Hallo All I once asked about SMUC, about ALTER emulation. I recently found some information about ALTER which is in SMUC MAX7000 family EPM7032 chip type, 32 macrocells, 600 valves, no triggers 36 user inputs/outputs, 178 MHz is the maximum frequency. Maybe someone is interested. Best wishes to you.

Hello, All! Somehow some information flew by, with questions about SMUC, The EEPROM chip is small, 24LC16, 16 kBit or 2 kByte. The alarm output is connected to the 6 interrupt controller IRQ0 The IRQ1 input is connected to the IDE connector, and ALTER. Inputs IRQ2, IRQ3 are connected to the ISA slot. Best regards, Dmitry Zaytsev.