Single ZX construct.
ZXNet echo conference «hardware.zx»
Hello, All
Single ZX construct.
I propose to use the basic ones as a single design for the ZX Spectrum
(i.e. minimum possible) standard sizes of ISA16 boards. In this case, the processor unit
place it not on the motherboard, but on the fatherboard. This will remove any
restrictions on the design of the computer. Those. for the same
basic ZX-fatherboard will be possible to install as in a classic
a small-sized spec case, or any of the standard PC line.
Computer design options.
1) Classic ZX Spectrum.
ZX-fatherboard built into classic flat housing, printed bus connector
NemoBus is used as an expansion bus and allows, through a slot in
connect external expansion devices to the rear wall of the case in the same way
to the original Spec;
2) AT/ATX version.
ZX-fatherboard plugs into a universal backplane with expansion connectors
ISA16. The versatility of such a backplane is determined by the possibility of installation in
AT, or in ATX cases and the presence of a dimensional grid of mounting holes
corresponding to both form factors. Universal crossplate is performed from 6-7
ISA16 connectors, into one of which the ZX-fatherboard is inserted, and the remaining
used for 5-6 additional expansion cards.
3) Slimcase design.
When used in Slim cases, the ZX-fatherboard is plugged into the backplanemade to fit the dimensional grid of the body being used.
4) 2 in 1 design.
For those who do not need a second PC coffin on the table, and who have a standard ATX
The case has a mATX motherboard installed, installation in the same case is possible
ZX-fatherboard into a special backplane for 3 ISA16 connectors. In this version
you can add only 2 expansion cards, which in most cases is quite
it is enough due to the execution as a unit with the PC (i.e. everything else is in the PC).
It is possible to design it in the form of a special basket for 4 ISA16 connectors inserted into
2x5.25" housing bays.
Functional features of ZX-fatherboard.
1) Functional composition.
Although theoretically you can put the entire computer with all of them on the ZX-fatherboard
controllers, I still think it’s not worth doing this, because not everyone needs it. Therefore
You only need to place generally necessary nodes:
- a processor unit with a standard one (at a minimum, but it can also be extended)
video processor;
- standard ZX interfaces: TAPE, SPEAKER, ZX-keyboard, Kempston Joystick,
Video, Sound (AY/2xAY+FM), NemoLPT, NemoBus;
- commonly used interfaces: COM, PS/2-keyboard & mouse,
ZX-IDE/CF(possibly SD);
2) Food.
- 2 standard PC connectors (+5V,G,G,+12V) spaced apart for greater uniformity
power supply;
3) Technological features.
- the mounting side is opposite to standard ISA cards;
- fiberglass thickness 1.6+/-0.2mm;4) Overall dimensions.
- minimum dimensions in depth - 167.1 mm (along the edge of the ISA16 connector);
- maximum possible dimensions in depth - 333.2 mm;
- maximum dimensions in height - 95.5 mm (excluding the protrusion of the ISA16 connector),
The ISA16 connector protrudes 7.6mm in height (dimensions are given according to the ISA standard
boards, but the height size can be larger and is practically limited only
body dimensions).
Functional features of backplanes.
1) Placement of connectors.
- connectors are placed relative to the windows for expansion cards in the case
similar to PCI connectors, which corresponds to the side of installation of elements and
eliminates the possibility of installing a ZX board by mistake into a standard ISA PC connector
(if there is a metal mounting strip), and also eliminates the possibility
installing ISA boards into the ZX backplane.
2) Food.
- 2 standard PC connectors (+5V,G,G,+12V) spaced apart for greater uniformity
power supply or one AT or ATX connector (must be routed on the backplane
all);
- AT/ATX connectors use only +5V, +12V, GND, PWGOOD contacts
(supplied as mounting OR according to the OK circuit in parallel to the reset driver on
ZX-fatherboard), PWON (output to the contacts for connecting the closing button with
fixation);
3) Overall dimensions for AT/ATX.
- 17 cm in the depth of the body, 15 cm along the windows for fastening strips.
Hello cr0acker
ISA16 you say? Pisism grew stronger...
Hello, Black_Cat
Re Black Cat:3) Slimcase version When used in Slim cases,
ZX-fatherboard is plugged into a backplane made to fit the dimensional grid
the body being used.
I like the idea
especially the possibility of abandoning ATX and other desktop coffins
and the ability to assemble a spec in a different package from those mentioned
As an example, you can look at this (not advertising!):
http://images.apple.com/macmini/images/designdimensions20060228.jpg
or
http://www.theapplecollection.com/design/macreleased/images/g4_cube_front.jpg
Hello, Black_Cat
Ubilnakh
Hello, Black_Cat
I have a hard time imagining IDE cables plugged into the fatherboard. :)
IMHO, a single construct is a motherboard on which absolutely everything is laid out
what is needed. And then everyone solders what they need there. And what is not needed -
does not solder.
Such a board can be published in larger quantities - cheaper.
This is exactly how they do things in China.
Hello NovaStorm
I liked the idea with FatherBoard... if the processor module is completed
separately, then it becomes possible to install several CPUs, naturally with
correct coordination of these...
There's a lot to think about here...
I like the design, I can test it in practice...
ZY The only thing I don't like is the installation difficulties
metal fastening strips, on which stable operation depends on the part
PC... or rather, it’s not the difficulty of installation, but the difficulty of getting them
somewhere...
I appeal to folk craftsmen... who have the opportunity to make in
factory-made metal strips in sufficient quantities and at reasonable prices
prices, or people who can simply get them - RESPOND...
Hello icebear
ice> industrial PC
industial IBM because it was basically distorted like this when it made comps on MCA,
but there’s nothing else besides the processor cache and the coprocessor
didn't install
Hello icebear
Well, you’re not small... Apparently that’s what makes them different =)
And there were already topics on the subject - mini-ITX is good for everyone. The new buildings are really not
as cheap as ATX.
Hello icebear
ice> how is Fatherboard different from Motherboard?
This is not miniITX, Fatherboard is a processor unit board (usually with
minimum required controllers) made in the form of an ISA board,
naturally does not have slots on itself but has a printed connector with which it
plugs into a backplane with expansion slots, i.e. in fact this is the half
Motherboard, on which the parts, and the backplane is that part of the Motherboard, on
which only slots. By the name - you understand the difference between dad and mom
:) - who bumps into whom.
Hello, captain cobalt
cap> I can hardly imagine IDE cables plugged into the fatherboard.
Fatherboard is a construct that exists with at least 286 processors, with
In this case, as a rule, on such a board all the minimally necessary
controllers - FDC, HDC, ports, video. I didn't invent anything - this
the construct is more than 15 years old.
cap> And what is not needed is not soldered.
This design, in addition to its maximum flexibility, is also very economical.
according to the consumption of fiberglass, because allows you to make ZX-fatherboard exactly like this
sizes as needed to accommodate the elements. As opposed to mATX format
binds the developer to the dimensional grid of this format and forces
overpay for extra fiberglass, as well as engage in breeding for
an empty place of unnecessary appendages.
Hello MegaMyth
Meg> I liked the idea with FatherBoard... if the processor module
Meg> is made separately, then it becomes possible to install several
Meg> CPU, naturally with proper coordination thereof...
Meg> There is something to think about here...
Meg> I like the design, it can be tested in practice...
Meg>
Meg> Z.Y. the only thing I don't like is the difficulties with
Meg> installation of metal fastening strips, from which part
Meg> the stable operation of the PC depends... or rather, not the complexity
Meg> installations, but the difficulty is to get them somewhere...
Meg>
Is this banter or what? The problem of coordinating multiple CPUs takes you less time,
what is the problem with manufacturing metal fastening strips??????????
Hello, Black_Cat
Bla> This is not miniITX, Fatherboard is a processor unit board (like
Bla> rule with the minimum necessary controllers) made in the form
Bla> ISA boards, which naturally do not have slots but have a printed circuit
Bla> connector with which it is plugged into the backplane with expansion slots, i.e.
Bla> is actually the half of the Motherboard on which the parts are, and
Bla> backplane is that part of the Motherboard that only has slots. By
Bla> name - you yourself understand how dad differs from mom :) - who is who
Bla> is stuck.
Is this the official name or did you come up with it yourself? From the description you say probably
about the so-called industrial PC
Hello, Black_Cat
Bla> Fatherboard is a construct that has existed since at least 286
Bla> processors, and as a rule, all of them were installed on such a board
Bla> minimum required controllers - FDC, HDC, ports, video. I'm nothing
I didn’t invent Bla> - this design is more than 15 years old.
I'm afraid to ask, how is Fatherboard different from Motherboard?
Hello, Black_Cat
Bla> This is the official name, at least it was so in the documentation
Bla> is written. Yes, they used to like to do industrial in such a design earlier
Bla> PC, but it was also common among personal computers. First time like this
Bla> personal computer I came across Nixdorf Computer 8810/60 (now it is
Bla> Siemens-Nixdorf or just Siemens :) ). German technology is
Bla> class - made for centuries.
Hmm, the only thing I found on Google for this term
http://www.bigfun.be/files/jpg/mother%20father%20board.jpg - where to read
more about Fatherboard?
Hello icebear
ice> where to read more about Fatherboard?
I doubt that there is such a special standard, by and large
design and signals - this is a regular ISA board, although some developers
got rid of it by adding more. ISA type connectors for communication with the same
non-standard ISA memory boards (usually on deeps). But this is already
special perversion. I can't say anything more.
Hello icebear
ice> Is this the official name or did you come up with it yourself? According to the description you
ice> you are probably talking about the so-called. industrial PC
This is the official name, at least that’s what it was written in the documentation.
Yes, they liked to make industrial PCs in this design before, but it was
It is also common among personal computers. For the first time I came across such a personal computer Nixdorf
Computer 8810/60 (now it is Siemens-Nicksdorf or just Siemens :)).
German technology is class - made for centuries.
fan> And ordering such a board specifically is simply senile, because
fan> will have to overpay twice, both to the manufacturer and
fan> to the consumer...
Fan, no one is forcing you to install a cross-plate. The ZX-fatherboard itself is ready-made
a minimally equipped computer similar to your Respect, but with a system
bus in the form of a printed connector as in the original Speck and it can be simply
So put it in the usual flat ZX cases.
fan> Z.Y. You need to strive for beauty
It’s absolutely the same thing here - CPU, memory, FPGA, connectors, well, AY, and then what?
the developer will decide, but in the first post I described what I understand as the minimum
modern configuration.
Hello icebear
ice> The problem of coordinating several CPUs takes you less than
ice> problem of manufacturing metal fastening strips??????????
Killed me :v2_lol; :v2_lol:; :v2_lol;
-+------------------------------------------------------------------------------
A similar nonsense idea came to me on the topic of using old
bits of motherboards (some have such a chic design that it’s enough
just remove the piece with the chipset :D), but preliminary examination showed
total shortage of them per capita :D. And order a special one like this
the fee is simply insane, because you have to overpay twice, as
both the manufacturer and the consumer...
ZY You need to strive for beauty -
http://www.amiga.org/modules/myalbum/photo.php?lid=2890&cid=13 :D if it's not
I like it, then this will certainly save the fathers of democracy ;) -
http://www.bazix.nl/onechipmsx.html
Hello fan
Well, for “single-chip” solutions and large boards are not needed. If the 12x12 doesn't roll
nano-itx, then 17x17 mini-itx should fit into almost any ATX box.
Multiprocessor Z80 systems are already unscientific fatalities. Therefore the benefits
"Fatherboard" ideas will most likely not exist in reality.
Hello icebear
To begin with, you can get strips in small quantities from computer companies
those involved in assembly - they have 1-2 pieces left from each assembled computer, in old ones
companies have deposits of these planks, but most of them have a relief surface, which
not very suitable, but it will go to extremes, just because they need more
corner brackets. You can also look at computer markets, although now
There is less and less such junk there. In general, such a mission, if there is one
insurmountable problems - it’s better to leave it to the user :), even if it’s a computer
amateur, but working with a file as a mechanic is not setting up electronics :) and
It’s more realistic for computer companies to shake up all over the country than in one city (except
Moscow and St. Petersburg). Although IBM was made in Zelenograd, was it really all imported?
Hello icebear
ice> Is this banter or what? The problem of coordinating multiple CPUs is smaller than you
ice> is concerned with the problem of manufacturing metal fasteners
ice> slats??????????
Believe me, this is how it is... my hands are not sharpened for working with a jigsaw...
Honestly... that’s why coordinating 2 CPUs is easier than working with a duster
Hello, Black_Cat
By connectors:
All the connectors won’t fit on the end of the ZX-fatherboard, so it makes sense to install them there
what is technologically easier to make holes for in a homemade plank and what
do not buy as a ready-made miscarriage. Here is a list of miscarriages with probability estimates
getting:
- COM 9pin - very common, from old ISA multicards;
- GAME 15pin - very common, from old ISA multicards;
- PS/2 - less common, from old AT motherboards;
- LPT 25pin - not very common, from old AT mmams;
- VGA 15pin - even less common, from old AT motherboards with video on board;
- Sound x3 - even less common, from old AT mothers with sound on
board;
Those. the most recent positions are the most rare, which means they are better
put directly on the board, and connect the rest through needles
connectors in the form of miscarriages. Those. maximum that can be squeezed onto the end
ZX-fatherboard is: VGA, PS/2 x2, Sound and TAPE (motherboards for 1.5mm plugs), or
Instead of PS/2 x2, install one CF or SD connector.
GAME and LPT are one standard miscarriage strip, COM,LPT,PS/2,VGA (in some places
GAME) can be screwed directly onto the body without a strip at all.
Thus, it remains to find brackets for the controllers, and these brackets are like
usually blind, they can be made from ordinary strips that go in spare parts to the body
screwing the corner brackets to them.
Hello, Black_Cat
Bla> ...the last positions are the most rare...
Why focus on old ones, you can also find them on modern mothers.
Hello MegaMyth
Meg> Believe me, this is how it is... my hands are not sharpened for work
Meg> with a jigsaw... honestly... so coordinating 2 CPUs is easier than work
Meg> cap
Scheme to the studio! With explanations. For example, I don’t know how to coordinate two CPUs,
although it is very interesting to look at the circuit and understand the principle of its operation. For this I
I will send you the planks in a quantity convenient for you. This is not banter, I'm completely serious.
I'm waiting for the diagram.
Hello, Black_Cat
Bla> This is not miniITX, Fatherboard is a processor unit board (like
Bla> rule with the minimum necessary controllers) made in the form
Bla> ISA boards, which naturally do not have slots but have a printed circuit
Bla> connector with which it is plugged into the backplane with expansion slots, i.e.
Bla> is actually the half of the Motherboard on which the parts are, and
Bla> backplane is that part of the Motherboard that only has slots. By
Bla> name - you yourself understand how dad differs from mom - who is who
Bla> is stuck.
This reminds me of this:
http://www.nedopc.org/nedopc/91/
Hello, acidrain
aci> This reminds me of this:
aci> http://www.nedopc.org/nedopc/91/
this is essentially an industrial pc :)
Hello, Error404
Err> And multiprocessor architecture is not needed at all - only resources
Err> spend on approval, and no one will write software for it.
Yes.. for multiprocessor structures the main problem is what exactly to program
It’s difficult for them.. but in terms of hardware it’s not all that sad
Hello icebear
ice> Scheme to the studio! With explanations. For example, I don’t know how to reconcile
ice> two CPUs, although it is very interesting to look at the circuit and understand its principle
ice> work. For this, I will send you strips in a quantity convenient for you. This is not
ice> banter, I'm completely serious. I'm waiting for the diagram.
What is there - do blade-farm right away :D: a bunch of loosely connected ZXs having
interface with the control board (PU, also ZX ;)) via PDP.
Accordingly, you can virtualize those connected to the control board
devices and interact (if necessary) through the same DAP channels:
ZX...ZX<->PU<->ZX...ZX
And there’s no need for a multiprocessor architecture - you just need to spend resources on
approval, and no one will write software for it. It's easier to run on one
uzi blade, on another vnc, which will draw uzi screens, on the third
- servicing the TCP/IP stack, on the fourth CP/M, and on the twentieth in DIZZI to wander. :)
Hello MegaMyth
I'm also for multi cpu ~!
Hello, Black_Cat
Bla> Although IBM was made in Zelenograd, was it really all imported?
Can you be more specific... which factory?
Hello icebear
ice> Scheme to the studio! With explanations. For example, I don’t know how to reconcile
ice> two CPUs, although it is very interesting to look at the circuit and understand its principle
ice> work. For this, I will send you strips in a quantity convenient for you. This is not
ice> banter, I'm completely serious. I'm waiting for the diagram.
It was necessary to immediately dot everything... the fact is that the Z80 is good
will not unite and this is a simple truth that does not need explanation... speech
was that it is possible to install additional processors
modules that will still be controlled by the main processor. module... implementation
multitasking is purely software, but with proper coding it will give an increase
productivity by 70-80 percent for each additional. CPU...
How to use this you ask? Yes, very simply...
1. set the sound to the auxiliary process - this is the process of steamed turnips.
2. the frame is being drawn and not completely... some of the static information can be
draw on additional process (status bar, etc.)
3. The picture is multi-layered.... first the additional process is given the task of drawing
let's say the background, at this time the first percent draws the foreground when they
both completed this procedure, the prots share the fate of memory and
are transferring layers to the screen at the same time...4. The program needs to read some information from the disk... the main processor instructs
helper to deal with this difficult task while he himself performs the operations,
which can be done without the participation of information located on the disk...
5. When playing a video, the 2nd percent is engaged in reading information, the 1st
unpacking/drawing the previous frame...
I repeat once again that such work requires a clear, balanced
program.
ZY It seems to me that having 4 21-28 MHz CPUs on board will be possible to create earlier
unprecedented miracles, since only one LDIR will be able to copy memory from
speed from 4 (at 21 MHz) to 5.34 (at 28 MHz) MB/sec... I would like to hear your opinion
programmers about this... do they need additional CPUs and will they be able (and
I'm sure they can) write programs for them?
Hello MegaMyth
We are talking about programming additional processors if these same processors
will be in 1 copy (well, even 1-2 dozen, and if there is an additional fee
(accelerator) which can be connected to any clone, and also what I wrote in
for the tasks being solved, it makes sense if the processors are 21-28 MHz in the case of 3.5-7 MHz processors
the meaning is lost (point 1 is finally supposed to be a separate article because in order for
so that he could steer with sound, he needs to organize the capture of the bus and write data to
port, and this is a big problem for existing clones)
Hello hero
If there is more than 1 percent, then it is therefore necessary to organize
bus access distribution. And in the clone models known to me, it is used
dynamic memory, which imposes some restrictions. Not for anyone
secret is that in most clones, at the moment the processor accesses memory,
generation of WAIT, which is a consequence of slow memory operation. Thus
There can be no talk about multiprocessing, although you can get twisted and do
Each processor has its own memory, but what about the devices? if everyone
additional processors will need to work with devices, then the head bus
at some point in time the person will be so busy that he will not be able to
execute commands. especially if everyone has their own memory, then it needs some kind of
way to forward... which will also take time, for which we are fighting...
Some rules follow from this:
1. The bus frequency must ensure operation of at least 2 percent and
video controller. since the Z80's minimum memory read cycle is 3 clock cycles, we
we get:
1 processor 28,000,000/3=9.33 MB/sec or 107 ns.
2 processors 2*28,000,000/3=18.66 MB/sec or 53 ns.
3 processors 3*28,000,000/3=28 MB/sec or 35 ns.
4 processors 4*28,000,000/3=37.33 MB/sec or 26 ns.
But there is also a video controller that should also be able to read frommemory and not slow down other processors. Maximum data flow output to
monitor is 7000000/8*2=2.5MB/sec in normal mode 256*192*1 bits per
pixel+1 attribute byte per 64 pixels, 3.5 Mb/sec at 320*200 4 bits per pixel, 7
MB/sec at 320*200 8 bits per pixel (BitPerPixel), and in the future there is also
640*480*60-75Hz*8BPP and this is not much, not little, but 25.175-31.500MB/sec.
By increasing the memory capacity to 16 bits (I hope not in the near future
16-bit modes will be required at a resolution of 640*480) and access time to
memory equal to 15ns (on which experiments are currently being carried out), then we
we get an average access time of 30 ns while drawing the main part
screen, and 15 ns when forming the border and sync pulses.
From here it is clear that in theory all this is possible, and I will try with all my might
implement (at least 2 percent).
2. Each processor must have its own memory addressing registers.
3. A conflict resolution system is required when accessing devices at least
at the software level.
4. It is necessary to wean software programmers from working with I/O ports
to the straight line. all work with devices ONLY THROUGH THE OPERATING SYSTEM
or, less preferably, through the driver, but although it is possible into the driver
build in an access distribution function.
Hello, Error404
Meg> If there is more than 1 percent, then it is therefore necessary
Meg> organize distribution of access to the bus.
Meg>
I think dividing one spec bus between several
Protsami is not good.
New processor modules (video, sound, computational axel)
need to be made as completely autonomous devices that communicate
through a channel (eg bus) with Spec's z80.
Each module has its own independent memory, bus and processor.
It also has a set of asynchronous commands
(after issuing a command to the module, the main z80 can immediately issue
next command to another module)
The programming ideology is as follows:
transfer data to the module memory and issue commands for their processing
A computational axel is, for example, a 60-megapixel workstation ($10) with a 10ns memory meter.
Hello Valen
Val> I
Val> New processor modules (video, sound, computational axel)
Val> should be made as completely autonomous devices that communicate
Val> via a channel (eg bus) with Spec's z80.
Val> Each module has its own independent memory, bus and processor.
Val> It also has a set of asynchronous commands
Val> (after issuing a command to the module, the master z80 can immediately issue
Val> next command to another module )
Val>
Val> The programming ideology is as follows:
Val> transfer data to the module memory and issue commands for processing it
Val>
Oh! The same as I suggested in the post above: v2_cheer; ,; only it's more private
case, it seemed to me. I am a supporter of equality :v2_finge; -; with such
architecture, any scarf can be loaded with any function - everything determines
onboard mathematics, which may well be downloadable via a hypervisor. And
any board can have access to any resources of the entire system.
Hello MegaMyth
Meg> If there is more than 1 percent, then it is therefore necessary
Meg> organize distribution of access to the bus.
Meg>
Meg> [...cut out calculations... ;) ]
Meg>
Meg> all work with devices ONLY THROUGH THE OPERATING SYSTEM
Meg> or, less preferably, through the driver, but although it is possible in
Meg> driver to build in access distribution function.
No, explain to me - why fence the garden? Build SMP or NUMA (whatever else
any smart words? :v2_tong; ); from something that is not intended for this. Not
it will work out. Everything will go “into the sand”, i.e. such a "multyZ80" car is unacceptably large
time will work on its own synchronization. And if you also consider
that 1 Z80 at the same time still only works with 64k of memory, then in general
the meaning is lost.
Make a better blade factory with one control hypervisor. As easy as shelling pears
- you just need to add interrupt and DMA services to each blade. And the algorithm
work will be simple and clear (as it has been for decades): in
depending on the required action to access an external device or other
blade, the blade will output to the port (i.e. to the bus of which it is included infactory) request, which is decrypted and routed by the hypervisor. Having given out
request to the queue, the blade continues to work on its task (or waits -
depending on which algorithm).
- If this is a request to external devices connected to the hypervisor, then it
considers the necessary data, placing it through the DDP directly into the requester’s buffer
blades, then give the blade the go-ahead signal for interruption - they say, food is served.
- If this is a request to access the memory of another blade (an option when one
a single-processor board prepares data for another, or some
software exchange channels when the software can take over more than one
blade), then the hypervisor will check this request for correctness (blade cards in
Depending on the software that runs on them, they may be registered differently in
hypervisor) and transfer the data.
- Other outputs/inputs such as keyboard or RGBI (i.e. console) are elementary
multiplexed into one channel by the same hypervisor (software selected
the console of one of the blades - the one on which you need to make some settings
or run something).
This, of course, is a little slower than multiprocessing, but nothing
need to be invented (PDP has been used for who knows how many years), absolutely
transparently logically - i.e. debugging will be many times faster, extensibility
just at the level of sticking the scarf into the slot, and the characteristics of the blades canbe different - even Leningrad1 :D, even ARM or 68k - as long as there is DMA/INT,
Yes, the software supported a compatible protocol.
Hello, Black_Cat
Bla> This would have happened a long time ago if tasks worked through the axis. And the axis is not
Bla> is used because there are not enough Spectrum resources. Not yet
Bla> of a fast machine, they will not use an axis (unless only in system ones
Bla> applications). HOW!!, I'm afraid that even when there is a fast car - an axle
Bla> will not be used anyway :) - they will simply use the additional one
Bla> performance to expand capabilities. Using the axis for
Bla> Spec will become the norm when it is most likely no longer possible for a programmer
Bla> or it will be very difficult to cope with overgrown hardware
Bla> resources at a low level.
Of the closest ones - there are a lot of CP/M (and, by the way, even MP/M) machines with the tact of a stone
1...2 MHz (and not even Z80, but weaker), which worked perfectly through the OS and with
screen, and with a keyboard and a disk drive, etc.
Working directly on the screen is acceptable for games under a single-tasking OS, the main thing is
so that the game does not destroy the OS kernel, and when exiting, restores the environment as it was
it was there at the start of the game.
Hello Valen
Val> fast specialized VDP (working in parallel with the main one
Val> percent)
This is not a solution, the goal is not to make a slot machine from the Spectrum, a gaming
The machine does not need an OS. We need universal solutions and a return to the old
states is a much more correct path, making the transition to universal
easier to use the OS.
Hello MegaMyth
Meg> 4. It is necessary to wean software programmers from working with ports
Meg> input output to direct line. all work with devices ONLY THROUGH
Meg> OPERATING SYSTEM FEATURES or, less preferably, through
Meg> driver, but although it is possible to build a distribution function into the driver
Meg> access.
This would have happened a long time ago if the tasks worked through the axis. But the axle is not used
because there are not enough Spectrum resources. Until there is a fast car, no
will also use the axis (unless only in system applications). HOW!!, I'm afraid
that even when there is a fast car, the axle will still not be used :) -
they will simply apply additional speed to expand capabilities.
Using an axis for Spec will become the norm when the programmer most likely already
it will be impossible or very difficult to cope with the overgrown hardware
resources at a low level.
Hello, Error404
We're talking about games - they work on the edge of the system's capabilities, and with the addition
processor speed will be added and advanced screen modes, which are
the performance will be eaten up and everything will return to normal. But about the return
previous state - this is probably the most optimal way, and to do it
The hardware method is even better. This has already been discussed:
http://zx.pk.ru/showthread.php?t=897.
Hello, Black_Cat
Bla> We’re talking about games - they work on the edge of the system’s capabilities, and with
Bla> by adding processor speed, advanced modes will be added
Bla> of the screen, which will eat up this performance and everything will return to normal
Bla> own.
Bla>
Gaming machine engineers solved this problem a long time ago.
Relatively low-power processor +
fast specialized VDP (working in parallel with the main processor)
= good result.
Hello, Black_Cat
Bla> This is not miniITX, Fatherboard is a processor unit board (like
Bla> rule with the minimum necessary controllers) made in the form
Bla> ISA boards, which naturally do not have slots but have a printed circuit
Bla> connector with which it is plugged into the backplane with expansion slots, i.e.
Bla> is actually the half of the Motherboard on which the parts are, and
Bla> backplane is that part of the Motherboard that only has slots. By
Bla> name - you yourself understand how dad differs from mom :) - who is who
Bla> is stuck.
I don’t know in what kind of DIY-Kulibin circles these boards are called
"phaserboards", and in industrial automation they are called MicroPC (sometimes
Slot-PC). Author once again demonstrated his ability to call
long-existing concepts (due to their own
ignorance must be assumed) and again this invention is presented as the only
correct and well known to everyone...
Hello Valen
2 Valen & Error404;
You; both propose to transfer data from one processor module to
to another, but I suggested using a single memory and a single
BB devices.
Provided that all processors have a single address space for both memory and
and input/output devices, and each processor has the ability to connect
any memory page in any 16K window and each processor has the ability
The following mechanism appears to manage the pages of any other processor:
1. The master processor sets the slave processor to the first 16k window,
let's say the first page of memory.
2. writes the JP routine command to it at address 0066
3. sends an NMI signal to the slave processor.
Sample code here - http://zx.pk.ru/attachment.php?attachmentid=4349&stc=1
["http://zx.pk.ru/attachment.php?attachmentid=4349&stc=1"]
Such a mechanism, in my opinion, will save you from sending a large amount of data.
Again such IMHO, which fundamentally goes against the concept
ZX-Spectrum.
File: untitled.gif http://zx.pk.ru/attachment.php?attachmentid=4349
Hello MegaMyth
Meg> can you be more specific... which plant?
At Kvante. http://scripts.online.ru/it/news/96/03/18_10.htm
Hello MegaMyth
Meg> 2 Valen & Error404;
Meg>; You both propose to deal with data transfer from one percent module
Meg> to another, but I suggested using a single memory and
Meg> single explosive devices.
Meg> Provided that all processors have a single address space as
Meg> memory and input/output devices, and each processor has
Meg> ability to connect any memory page to any 16K window and
Meg> each processor has the ability to manage the pages of any
Meg> of another processor the following mechanism appears:
Meg> 1. The master processor sets the slave processor to the first 16k
Meg> window, say, the first page of memory.
Meg> 2. writes the JP routine command to it at address 0066
Meg> 3. sends an NMI signal to the slave processor.
Meg> Such a mechanism, in my opinion, will save you from sending large volumes
Meg> data.
Meg> Again such IMHO, which fundamentally goes against
Meg> concept of ZX-Spectrum.I'm afraid it will all end either in glitches because in "my" memory it is unceremoniously
someone else writes (and otherwise - in the case of an allocated buffer -
how is this different from PDP?)
or a monstrous hardware synchronizer (how to separate processors to
didn't they modify the same memory/ports at the same time?
Software? So this is until the first error, which will take out the ENTIRE system, because...
the address space is shared). How to insure that the window is turned on by the dispatcher
Doesn't one processor overlap something needed by another? Even assuming that it is
you can check at the current moment, but what if this memory is needed by the second
after a couple of cycles, and the dispatcher is already turned on and the memory is being used? In line,
Waits, etc. Or you need a processor cache, which is not provided at all in the Z80.
The gains from shared memory are lost.
Hello, Error404
Err> how to separate processors so that they do not modify into the same one
Err> time same memory/ports
I'll try it and tell you.
Hello MegaMyth
Separating the prots is not so difficult... how to bring them together :)
I’ll probably try using the ZX-Polyhedron emulsion this holidays, otherwise it’s old
sowed..