memory

Hello Kirill! 03 Apr 00 00:31, Kirill Frolov -> Viktor Vorobov: [skipped] KF> When the yellow scorpion board first appeared for me, then there for KF> for six months a lot of logic chips flew out and I got tired of them KF> resolder. But then there were almost no breakdowns in 4 years, excluding bumps KF> - once every six months or a year they fly out 1 piece. :-( maybe you have some wild nutritional quirks? It’s just that this is the first time I’ve heard the memory disappear so consistently... My computer has been plowing for so long (10-12 hours a day) and nothing crashes... for now :) In fact, look at the power supply. Alexand

Hello, Viktor! Somehow 05/14/00 at 00:44:40 Viktor Vorobov wrote to Yura Nazarenko on the topic of "memory"... YN>> The guy had a meter (like 6.7 bit port #1ffd), so Real YN>> Commander (RC) gave about 1800 seconds of free memory. At my place YN>> 512, so it also gives 1800 seconds. VV> So maybe he didn’t connect it correctly, that thread is still this VV> video meter? Well, he had (now I have) 6.7 bit #7ffd, and because of this, terrible buggy programs that click pages through out (#fd),81. Now I changed it to #1ffd, and even RC shows 3915. IMHO the meter is a rule!! All the best to you, Viktor! Yuri Nazarenko/Rezident/N-Discovery e-mail: Yura_Nazarenko.sp0251@zxnet.spb.ru

Press RESET immediately, Yuri! 01 Jun 00 20:38, Yuri Teslenko wrote to Yura Nazarenko: YN>> Well 6&7 additional memory (except 128 and 256kb)! 6th bit 512, YN>> 7th bit 1024 YT> Well, damn it... YT> 0,1,2 -128k YT> 3 - screen YT> 4 - ROM YT> 5 - lock (256) YT> 6 - 256k (512) YT> 7 - 512k (1024) YT> Where can you get 1024? Except for the lock. 4 bits from 1FFD. Scorpio people always forget that besides the poor Scorpio There are more other spectra.

Howdy, Kirill! 3.06.2000 at 01:15 Kirill Frolov wrote to Yuri Teslenko: YT>> Bullshit :) Better on logic - so to speak, always on time :) TM2, YT>> LE1. KF> Logic is difficult. The delay must be done exactly at 32 clock cycles. It's not difficult. There is no need to make delays. KF> I don’t need to suggest how it’s done in KAY - demos don’t work there. I don’t know how it works, but my demos still work, the ones that hung before: ___ V1<-----------|1 | _______ ___ | o--------o S|TT|Q|--->-INT -M1<---|1 o---| | +5v<--o R| | | -IORQ<---| | ~~~ |--| | | ~~~KS<--/ C| | | ,--| D| | | ~~~ ~~~~~~~ V1 - from the video controller, in the Pentagon it’s like b7 KF> And everything was done with capacitors, why redo it if you can KF> just solder the diode? I had 2 resistors, a diode, a capacitor - even with a mode toggle switch. But in mind Possible turbocharging was done using logic, so as not to “float away”. Bye, Yuri. [I.ZX] [Chemists] [For full address] [Ski poles] /_500:322/33@ZXNet_/ /_dangercorp@bigfoot.com_/ /_dangercorp@mail.ru_/ /_2:462/93.33@FidoNet_/

Press RESET immediately, Yuri! 05 Jun 00 21:10, Yuri Teslenko wrote to Kirill Frolov: KF>>>> Will NOT be read. The register output to the bus is not connected. YT>>> That’s not what we’re talking about... I’ll take LP11 and put it on and read it, eh YT>>> I won’t start -rd :) KF>> And there will be glitches. IORQ and WR are not synchronous signals on the bus. YT> They won’t, the AU is readable :) -M1 will save the father of Russian democracy :)) For me, when I connected the watch, it was like the watch stood still while I was trying to count the time from them and they walked forward normally until they there were no requests. And why - in the read cycle from the microcircuit, in that the point in time when the RD signal was already removed from the bus, and IORQ still remained The value that was just read from the clock was being written back to the clock! (there is more load on IORQ plus decryption delays) You cannot rely on the IORQ and RD or WR signals being synchronous. Moreover, that they are not actually synchronous on some processors. And also a delay switching decryptors up to tens of nanoseconds. You can't use logic which means that if there is no signal at the time of access to the port writing, then reading takes place, and vice versa. M1 signal in confirmation cycle Of course, I took into account the masked interruption.Think about why there are 2 signals READ and WRITE, and not one, like on motorolas all sorts of things. But because they appear not before the appearance of IORQ or MREQ, but synchronously (if +/- ~20ns can be called that). And it is not possible to decrypt record requests and reading do not use one of the signals, otherwise there will be false alarms at the end of each cycle. For example, for a watch or modem this can simply lead to to their inoperability. This is simply not noticeable on the AY chip, and even the microcircuit is so slow that it simply does not cause this false operation notices. In the Scorpio computer, you know why the outputs of the decoder connected to alter and those controlling the turbo mode switching solder capacitors ~1nF? But because their decoding is faulty about records in 7FFD and 1FFD and at the end Each cycle, a short reading pulse is obtained and the turbo turns off ;-( If you’ve been on zxnet for a long time and regularly read this echo, then you probably remember How often have people asked here why the turbo turns off in a Scorpio? In the book it is written in Russian in white - decryption is carried out unification by "AND" signals IORQ AND RD, and IORQ AND WR. And only this way, and no other way.

Howdy, Alexandr! 6.07.2000 at 00:29 Alexandr Kushnikov wrote to Dmitriy Nesmachny: AK>>> And /IORQGE is /IORQ after 20kOhm from the 20th leg of the processor. So? AK>>> Well, at least it’s like that on Scorp and Kai. DN>> What is the point of this summary? AK> I can’t say for sure, but I think that at the moment when /IORQ will be AK> is logical 1, then /IORQGE will be logical zero. Y? When the controller is disabled and -OUT IORQ is not generated, it is necessary that the ports were chosen, so -IORQ goes through this summary. When is the controller available? The summary eliminates the conflict, but is essentially unnecessary. Bye, Yuri. [I.ZX] [Chemists] [For full address] [Ski poles] /_500:322/33@ZXNet_/ /_dangercorp@bigfoot.com_/ /_dangercorp@mail.ru_/ /_2:462/93.33@FidoNet_/