Lame question about Z80 tire timing charts
ZXNet echo conference «hardware.zx»
Hello, boo_boo
even on the leading edge of WR, the clock still advances until the data passes through all
multiplexer triggers will reach the screen
Hello, boo_boo
boo> I’ve never dealt with a subject before, so I want to clarify, because I haven’t
boo> I'm sure I understood correctly...
boo>
boo> 1) writing to memory: 3 cycles (without WAIT), on the 1st clock cycle on the data bus
boo> a byte is formed, by the end of the second WR is activated, that is, this byte
boo> is ready, and you can shove it into memory.
boo>
boo> 2) writing to the port: 3 cycles + 1 wait, on the 2nd cycle WR is activated --
boo> the byte is ready (and hangs on the bus for another clock and a half)
boo>
boo> that is, in the case of a Spectrum without WAITs, the byte will end up in memory k
boo> at the end of the second clock cycle of the memory write operation, and when writing to the port -
boo> the device will also take it on the second (or third?) cycle...
boo>
boo> however, UnrealSpeccy, emulating out, waits only 7 clock cycles before recording
boo> to the port (that is, it does everything on the 1st measure), and the border effects work
boo> as it should...
This is... rtfm or something. If the latch catches the byte all the time that /WR is active, then so be it.
And if on the falling edge /WR? So much for 7 bars.