I studied the book on z80

Hello hero her> Show me the 4 byte op code, and for the 2 byte op codes M1 her> generated for EACH OPERATION CODE byte There are also such, i.e. extended, although for extended CB, ED, DD and FD another M1 cycle is produced. In normal mode, the command is retrieved in 4 seconds tact, but then the picture changes. Whites, writing, reading - they also suck bars. The error on interrupt confirmation is ~50, but IORQ can be subtracted. If we go further, then based on this we can determine in what modes performance is measured by linking to a clock and counting useful and lost cycles depending on who pulls the processor. All circuits for debugging processor devices are built precisely on this principle. B one, described in the "radio amateur", there is the possibility of step-by-step and cyclic debugging devices on Z80. It's clear what's going on. In the future, you can hang multichannel analyzer with a couple of dozen channels and already performs well speed, enter the data into Excel, and analyze it there. z.y. By the way, a phrase flashed here about eZ80 clocking, i.e. operations in one cycle are they readable? Strange, that means I didn’t look at the datasheet properly.