[FWD] Fw: ZX-VGA Converter

From Maxim Timonin: === Cut === Now let's get down to business: I'm here with Chunin Roman (owner Sprinter) we make an RGB2SVGA converter. We have prepared the text in which describes the principles of the future board. Could you throw it’s on Fido for people to look at and discuss. Maybe some glitches will they find it? === Cut === === Cut === 1. ZX-VGA converter 1.1. A little about signals. TV picture: 768x576 interlaced (interlaced) image scanning. 25Hz (50Hz for half frames). VGA image: 800x600 progressive (line-by-line) scanned image. 60,72,75,85,100Hz. When constructing an image in ZX, half-frames are not used, i.e. the picture is built completely in each half-frame (this is why the number of points is limited to 768x288, and if you remove all invisible parts are also 702x256). Folded synchronization is also used, i.e. frame (vertical) and line (horizontal) synchronization is supplied to one input. VGA uses different inputs for horizontal and vertical sync. Moreover, there are different modes (defined by the VESA standard) at which the polarity of these signals may be different. For example, consider the 800x600 60Hz mode: ? pixel frequency 40 MHz; ? horizontal front clearance (after finishing horizontal sync pulse and the beginning of the visible part of the line)40 pixels; ? horizontal sync 128 pixels and positive polarity; ? horizontal back gap (after the end of the visible part and the beginning of the horizontal sync pulse) 88 pixels; ? vertical front gap (after the end of the vertical sync pulse and the beginning of visible lines of the image) 1 line; ? vertical sync pulse 4 lines and positive polarity; ? vertical back gap (after the end of visible lines images and the beginning of the vertical sync pulse) 23 lines; Obviously, the pixel frequency (the frequency at which it changes) information about the minimum part of the image) differs significantly. In case we want minimal rework (and possibly without alterations) on the ZX output channel of the computer and preferably with maintaining capabilities (output to a TV compatible monitor), then the most reasonable choice would be a device called 'framebuffer'. 1.2. What is a 'frame buffer'? This means a device that has memory for saving one frame (and in the format that outputs this frame computer, i.e. ZX), then after appropriate transformations to the receiving device format (VGA). The advantages of this approach: ? no need to rework the ZX output channel and accordingly, maintaining all possibilities;? possibility of simultaneous work both on the TV monitor and to VGA; ? saving 'border graphics effects'; ? lack of additional digital-to-analog conversions; Disadvantages of this approach: ? with separate frequency generators - it is impossible to achieve smooth display of fast moving parts of the image (for To do this, you need to use one reference frequency generator, like computer and the converter, and calculate the path accordingly for this frequency); ? the effect of large (square) pixels, i.e. due to different resolution will have to use duplication lines and duplicating pixels in a line to get proportionate image. Since the computer was originally designed for TV, then accordingly, only the image on it will be ideal. Perhaps a model designed for VGA will appear soon, but this there will be a completely different computer, and its timings will be completely others, and accordingly a lot of software, using these features will either have to be rewritten or throw it away. The objectives of achieving the highest possible quality in our case it's not worth it. The task is to achieve the ability to display on VGA with minimal modifications (and price). Therefore, I believe that This method will give the best results. 1.3. Functional diagram [follows in UUE further]The above diagram is a simplified diagram classic 'frame buffer'. First, I’ll explain the basic concepts, and then we’ll look at the diagram for blocks: ? RGB digital signal is a signal that is converted into analog for display. For example, at the Pentagon 128 this is a signal is removed from two KP12 microcircuits that generate the signal R, G, B and Y(brightness); ? Pixel synchronization is a signal that informs about pixel change; ? Horizontal (horizontal) sync is a signal that informs about a line change; ? Vertical (frame) synchronization is a signal that informs about a frame change. All these signals are available on ZX clones, since they are collected on ordinary logical elements, you just need to dig carefully in the diagram. Unfortunately, if high-quality chips are used integration or programmable matrices, then some signals may be missing. In this case, you will have to add additional analyzing blocks in the circuit. Since in Russia branded models have not received much distribution, then this the issue will not be considered. Now let's briefly look at the operation of the device: ? Input register - used to remember the last states of digital RGB ZX signals. Clicks information on pixel sync signal from ZX. Its capacity dependsfrom the organization of the output channel of a specific ZX clone (for Pentagon 4 bits, ATM 6 bits), but usually eight bits enough for all clones (except Sprinter, he needs 24 bit since it supports TRUECOLOR). ? TV address counter - for each pixel of the displayed the surface is allocated one cell in the buffer memory. Address is counted from the beginning of the frame (i.e., essentially vertical synchronization is a reset signal for the counter) and for every pixel. I should immediately note that the curb information is also read pixel by pixel (this is necessary to save effects border graphics). Many clones use multiple screen modes, when the display line accounts for different number of pixels (for example, CP/M Profi screen and regular ZX screen), a horizontal synchronization signal is useful for this, which will count the width of the displayed area (just click on the address value on the first line - this is will be the width of the screen). But the question is still open, it’s more logical use independent pixel synchronization built from the frequency-setting circuit of the computer, then regardless of the logical screen width will have the same number of pixels. ? VGA address counter - this counter operates from an independentreference frequency generator for VGA. Frequency reference generator selected based on the VGA pixel frequency (for example, for 800x600 60Hz - 40MHz). Based on the values of this counter, timing signals for VGA. Also for the visible area counter value displays are used to obtain the address pixel in buffer memory. ? Control signal generator - generates all signals for control blocks, except for the input register and address counter TV. This block is responsible for general control of the circuit. Manages address multiplexer, signals for writing/reading information in buffer memory, controls the output register. Signals are being built based on the reference frequency oscillator signal. ? Address multiplexer - during a memory write cycle it connects address from the TV address counter, and during a read cycle from memory connects the address from the VGA address counter. ? Buffer memory - capacity is calculated quite easily: TV screen width (768) * number of TV lines in a half-frame (288). Although I would like to know more accurate values ​​from experts. But in any case, 256 KB of memory is enough. Unfortunately if decide 'head on'