DMA.

Suppose it is possible to implement DMA additional iron, how to do this well, on logical level, what would be convenient, and will it be justified? By the way, in the iron version, this copying will occur from the 1st clock cycle per byte: for two microcircuits, which is always the case, up to: quantity memory chips divided by two (for example, for 8 chips in 4 times), while all this is done in parallel with the processor (at the processor will have priority, or you can suspend, but this, in my opinion, is worse, but it won’t be necessary monitor the completion of copying, and during interruption forcefully transfer to background copying). So, what any suggestions? KIA