Connecting IDE screws to Spectrums

_-~ Greetings to you, All ! For quite a long time, the development of the sabzhe scheme took place. The device was developed as an alternative to the SMUC device. While the circuit is assembled on the breadboard and MGTF, in Yekaterinburg there are quite a lot of people interested in this device. Before making a signet, I would like to listen to the thoughts of the omniscient ALL about this issue. To get started: Main properties, hardware features: 1. MS-DOS file system 2. Ability to work with TR-DOS at level #3D13 (speed - high) 3. Screw loading possible 4. HDD port range: xx90h-xx9fh 5. To eliminate conflicts, enter /IORQGE /IORQGE=/IORQ | (A7 & A4 & /A6 & /A5) 6. There is ms 62256-621024 (in the latter case, you can disable the ROM completely. ), in particular, this allows you to work with the screw in TR-DOS (emulation #3D13, sector buffering 512<->256) 4. When working with a screw in TR-DOS, you can assign *.TRD disk images (of course, no more than 4 at a time). ^^^^^^^^^^^^^^^^^this^^^^^already^^^^^^^^^^is^^^^^^^^^^^^^ 7. Possible implementation in the future: - second IDE port - universal serial controller (I2C, RS232, USB) - I2C realtime clock DS1307 (dip08) Why I2C? I have already dealt with this watch, as well as with the 512vi1 For 512vi1 it was necessary to make a relatively complex anti-distortion blocking circuit information when on/off. And here everything is inside.estimated price < 10$ QUESTION: - What are the current IDE port layouts? ~-_ Well, All, be it. Eugene Stakhov Sunday 1 May 2000 13:34:43 [] [STUDIO STALL] [STD2] [QUORUM]

Greetings, O venerable Eugene! [Monday 1 May 2000] at [13:34:43] Eugene Stahov wrote a letter to All. They discussed the topic "Connecting IDE screws to Spectrums." Let's continue what we started... [skip] ES> QUESTION: ES> - what are the current IDE port layouts? ================== begin of file "NemoHDD .C" ================== DATL EQU #10 ;10: Data register low byte DATH EQU DATL+1 ;11: Data register high byte ERRF EQU DATL+#20 ;31:Error Rg SCNT EQU ERRF+#20 ;51:Pg sector counter SNMB EQU SCNT+#20 ;71: Sector no. CYLL EQU SNMB+#20 ;91:Rg cylinder no. (junior) CYLH EQU CYLL+#20 ;B1: Cylinder no. (major) SDH EQU CYLH+#20 ;D1: Drive and head no. RSTA EQU SDH+#20 ;F1:Pr state RCOM EQU RSTA ;F1:Rg commands ASR EQU #C8 ;Alter Stat Rg FDR EQU #C8 ;Fixed disk Rg DIR EQU #E8 ;Dig In Rg SYSR EQU #F8 ;sys rg . ================== end of file "NemoHDD .C" ================== Best regards, Felix. [I.ZX]

Greetings, Kirill! <12:46> Kirill Frolov write to Ivan Mak: IM>> I’ve already posted the diagram here, if necessary, I’ll repeat it. KF> Repeat, otherwise something is not clear... === Cut === ╔═══════════════════════════════ ═════════╦══════════════════════╗ ║ ║ Designed by Ivan Mak ║ ║ Sprinter HDD controller. Version 1.02. ║ FIDO: 2:5030/529.24 ║ ║ ║ (C) 1999 Peters-Plus ║ ╠═══════════════════════════════ ═════════╩══════════════════════╣ ║ The diagram is intended for possible repetition and installation on ║ ║ computers like ZX-Spectrum, as well as for understanding logic ║ ║ HDD operation of a Sprinter computer ║ ╠═══════════════════════════════ ════════════════════════════════╣ ║ "Buffers" ║ ║ K555AP6 ║ ║ ┌──┬────┬──┐ ║ ║ D0──────┤D0│ RG │Q0├────────────────── ─────────────────┬─WD0 ║ ║ D1──────┤D1│ │Q1├────────────────── ────────────────┬──WD1 ║ ║ D2──────┤D2│ │Q2├────────────────── ───────────────┬───WD2 ║ ║ D3──────┤D3│ │Q3├────────────────── ──────────────┬────WD3 ║ ║ D4──────┤D4│ │Q4├────────────────── ─────────────┬─────WD4 ║D5 D6 D7 ║ ├──┤ │ │ ││││││││ ║ ║ /RD───┤<>│ │ │ ││││││││ ║ ║ DIR1──┤OE│ │ │ ││││││││ ║ ║ └──┴────┴──┘ ││││││││ ║ ║ K555AP6 K555IR23 ││││││││ ║ ║ ┌──┬────┬──┐ ┌──┬────┬──┐ │││││││││ ║ ║ D0──────┤┤D0│ RG │Q0├────────┬────────┤D0│ RG │Q0├────────┘ ║ D1 D2 D3 D4 ║ D5───────┤D5│ │Q5├───┬────────────┤D5│ │Q5├───┘ ║ D6 D7 ║ ├──┤ │ │ ││││││││ ├──┤ │ │ ║ ║ VCC──┤<>│ │ │ ││││││││DIR3──┤WR│ │ │ ║ ║ /WR──┤OE│ │ │ ││││││││DIR2──┤OE│ │ │ ║ ║ └──┴────┴──┘ ││││││││ └──┴────┴──┘ ║║ ││││││││ ║ ║ │││││││└────────────────────────────WD8 ║ ║ ││││││└─────────────────────────────WD9 ║ ║ │││││└──────────────────────────────WD10 ║ ║ ││││└───────────────────────────────WD11 ║ ║ │││└────────────────────────────────WD12 ║ ║ ││└─────────────────────────────────WD13 ║ ║ │└──────────────────────────────────WD14 ║ ║ └───────────────────────────────────WD15 ║ ║ ║ ╠═══════════════════════════════════════════════════════════════╣ ║ ║ ║ "Схема, вшиваемая в ПЛМ" ┌─────────────────────DIR3 ║ ║ │ ┌──┐ ║ ║ ┌───/HDD_ENABLE─────┬─┴───┤1 ├──────────/HDD_CS1 ║ ║ │ ┌──┐ │ ┌───┤ │ ║ ║ ├─┤1 ├─────┐ │ │ ├──┤ ║ ║ /WR──────────│─┤ │ │ ├─│───┤1 ├──────────/HDD_CS3 ║ ║ │ ├──┤ │ │ │ ┌─┤ │ ║ ║ ├─┤1 ├───┐ │ │ │ │ └──┘ ║ ║ /RD──────────│─┤ │ │ │ │ │ └──────┐ ║║ │ └──┘ │ │ │ │ ┌──┐ │ ║ ║ └──────┐ │ │ ┌──────│─┴───┤1 o─┘ ║ ║ │ │ │ │ │ └──┘ ║ ║ │ │ │ │ │ ║ ║ ┌──┐ ┌──┐ │ │ │ │ ├────────────┐ ║ ║ /WR───┤& ├─────┤1 ├─┘ │ │ │ │ │ ║ ║ /RD───┤ │ ┌─┤ │ │ │ │ │ ┌──┐ │ ║ ║ └──┘ │ └──┘ │ │ │ └─────┤1 │ │ ║ ║ │ │ │ │ ┌──────────┤ ├─┐ │ ║ ║ │ │ │ │ │ WRH └──┘ │ │ ║ ║ │ ┌──┐ │ │ │ │ ┌──┬────┬──┐ │ │ ┌──┐ ║ ║ A8──────┬────│─┤1 o───│─│─│─┤ ┤S │ TT │ │ │ └─┤1 ├─────DIR1 ║ ║ │ │ └──┘ │ │ │ │ ├──┤ │ Q├──│───┤ │ ║ ║ │ └──────┐ │ │ │ ├─┤D │ │ │ │ ├──┤ ║ ║ │ ┌──┐ │ │ ├─│─┼─>C │ │ _│ └───┤1 ├─────DIR2 ║ ║ /IORQ───│──────┤1 │ │ │ │ │ │ ├──┤ │ Qo┐ ┌┤ │ ║ ║ │ ┌─┤ ├─┘ ├─│─│─│─┤R │ │ ││ │└──┘ ║ ║ │ │ └──┘ │ │ │ │ └──┴────┴──┘│┌──┐│ ║ ║ │ └──────┐ │ │ │ │ └┤& ├┘ ║ ║ │ │ └─│─│─│─────┬────────┤ │ ║ ║ │ │ │ │ │ │ └──┘ ║ ║ │ │ │ │ │ │ ┌──┐ ║ ║ │ │ │ │ │ └─────────────┤1 │ ║ ║ └───────────│───│─│─│───────────────────┤ ├──/HDD_RD ║ ║ │ │ │ │ └──┘ ║ ║ ┌──┐ ┌──┐ │ │ │ │ ┌──┐ ║ ║ A1────┤& o─────┤& o─┘ │ │ └──────────┤1 ├───────────/HDD_WR ║ ║ A2────┤ │ ┌───┤ │ └─│────────────┤ │ ║ ║ ├──┤ │ ┌─┤ │ │ └──┘ ║ ║ A5────┤1 ├─┘ │ └──┘ │ ║ ║ A7────┤ │ │ │ ║ ║ └──┘ │ │ ┌──┐ ║ ║ A6───────────┘ │ A0────────┤1 ├─────────────HD_A0 ║ ║ │ ├──┤ ║ ║ ┌──┐ ┌──┐ │ A1────────┤1 ├─────────────HD_A1 ║ ║ A1────┤1 ├─────┤& ├───────│────────┬───┤ │ ║ ║ A2────┤ │ ┌───┤ │ │ │ ├──┤ ║ ║ └──┘ │ ├──┤ │ A2────│───┤1 ├─────────────HD_A2 ║ ║ A14────────┴───┤& ├───────┘ └───┤ │ ║ ║ A2─────────────┤ │ └──┘ ║ ║ └──┘ ║ ║ ═════════════════════════════════════════════════════════════ ║ ║ Here only the logic in the PLM is drawn. ║ ║ The actual implementation is fundamentally different from the one drawn, ║ ║ since PLM allows you to implement complex functions on one ║ ║ cell. In addition, port addressing is done through the ║ ║ Sprinter port distribution, which allows you to change ║ ║ all hard drive port addresses. ║ ║ When repeating, it is enough to repeat only the logic and ensure║ ║ absence of "glitches". ║ ║ In addition, an additional delay from the beginning of /IO║ has been introduced into the PLM ║ since in TURBO mode at 21MHz they do not have time to install ║ ║ hard drive port addresses. ║ ║ Pins /HDD_WR,/HDD_RD,/HDD_CS1,/HDD_CS3 are fed to the IDE connector ║ ║ through resistance 150 ohms. ║ ║ The /HD_RES signal can be connected or not connected to reset ║ ║ computer. It's better not to connect, but some hard drives ║ ║ can seriously “shut up” if you work with them incorrectly and ║ ║ they may need an iron reset. ║ ║ An LED is connected to the /PDIAG signal through a 300 ohm resistor on ║ ║ +5v to indicate HDD operation. (but sometimes the LED lights up ║ ║ anyhow, especially with old hard drives and in SLAVE mode ║ ║ The /HD_RDY signal is either connected or not connected to ║║ /WAIT processor. It is better to connect via element AND with signal ║ ║ going to this processor pin from the computer circuit. ║ ║ ══════════════════════════════ ═══════════════════════════════ ║ ║ Wiring of 40-pin HDD connector ║ ║ ┌──────────┬───────┬────────── ┬───────────┐┌────────────────┐ ║ ║ │1 /HD_RES│11 WD3 │21 --- │31 --- ││ │ ║ ║ │2 GND │12 WD12│22 GND │32 --- ││ "pins" │ ║ ║ │3 WD7 │13 WD2 │23 /HDD_WR│33 HD_A1 ││ on board │ ║ ║ │4 WD8 │14 WD13│24 GND │34 --- ││ for cable │ ║ ║ │5 WD6 │15 WD1 │25 /HDD_RD│35 HD_A0 ││ │ ║ ║ │6 WD9 │16 WD14│26 GND │36 HD_A2 ││ 246 40 │ ║ ║ │7 WD5 │17 WD0 │27 /HD_RDY│37 /HDD_CS1││ ooo........o │ ║ ║ │8 WD10 │18 WD15│28 --- │38 /HDD_CS3││ ooo........o │ ║ ║ │9 WD4 │19 GND │29 --- │39 /PDIAG ││ 135 39 │ ║ ║ │10 WD11 │20 --- │30 GND │40 GND ││ │ ║ ║ └──────────┴───────┴────────── ┴───────────┘└────────────────┘ ║ ║ ══════════════════════════════ ═══════════════════════════════ ║ ║ The diagram works on Sprinter, but in the drawing itself ║ ║ inaccuracies. ║ ║ ══════════════════════════════ ═════════╦═════════════════════ ║ ║ HDD ports: xx50h..xx55h ║ Sector reading: ║║ xx50h - data port ║ CALL HDD_READY ║ ║ 0051h - error/precompensation port ║ JR C,ERROR ║ ║ 0052h - port number of sectors ║ LD BC,0050h ║ ║ 0053h - sector number port ║ INI..INI ; 512 times ║ ║ 0054h - port of the cylinder number, junior ║ RET ║ ║ 0055h - port of the cylinder number, senior ╠═════════════════════ ║ ║ 4052h - drive port/head number ║ Recording sector: ║ ║ 4053h - command/status register port ║ CALL HDD_READY ║ ║ 4054h - port port 3F6h ║ JR C,ERROR ║ ║ 4055h - port port 3F7h ║ LD BC,0150h ║ ║ When writing to a port, its address must be ║ OUTI..OUTI ; 512 times ║ ║ increase by 100h ║ RET ║ ║ ══════════════════════════════ ═════════╩═════════════════════ ║ ╠═══════════════════════════════ ════════════════════════════════╣ ║ How does the scheme work? ║ ║ ║ ║ Z80 ┌───┐ ║ ║ bus │Buf│ ║ ║ ──┬──┤<─>├────────────┬──<─> Low Byte ║ ║ │ │ 1 │ │ ║ ║ │ ├───┤ ┌───┐ │ ║║ │ │Buf│ │Reg│ │ ║ ║ └──┤──>├──┬──┤──>├──┘ HDD bus ║ ║ │ 2 │ │ │ 3 │ ║ ║ └───┘ │ └───┘ ║ ║ │ ║ ║ └────────────<─> High Byte ║ ║ ║ ║ 1. Read all registers except data register, A8 = 0 ║ ║ Data from the HDD bus is transferred to the processor through buffer 1. ║ ║ Only the low byte, the high byte is not needed. ║ ║ ║ ║ 2.1 Read data register, A8 = 0 ║ ║ Data from the HDD bus is transferred to the processor through buffer 1. ║ ║ Only the low byte, the high byte is needed and it is latched into ║ ║ register 3 ║ ║ ║ ║ 2.2 Read data register, A8 = 1 ║ ║ Data from register 3 is transmitted through buffer 1 to the processor. ║ ║ - high byte - HDD is not selected at this moment ║ ║ ║ ║ 3. Write all registers except the data register, A8 = 1 ║║ Data from the Z80 bus is transferred through buffer 1 to the HDD bus. ║ ║ Only the low byte, the high byte is not needed. ║ ║ ║ ║ 4.1 Write data register, A8 = 0 ║ ║ Data from the Z80 bus is transferred through buffer 2 to register 3. ║ ║ Only the low byte, the high byte is needed and is expected in the next ║ ║ cycle. The HDD is not selected at this moment. ║ ║ ║ ║ 4.2 Write data register, A8 = 1 ║ ║ Data from register 3 is transferred to the HDD bus - low byte. ║ ║ - high byte - transmitted through buffer 2 from the processor ║ ║ ║ ║ Why is paragraph 4.2 different from 3, although the operations are by type ║ ║ are the same? ║ ║ Because before 4.2 there is always 4.1, which installs ║ ║ trigger WRH to one and thus switches the path ║ ║ passing bytes. This allows you to use OUTI ║ commands ║ to write a sector to the HDD ║ ║ ║ ╚═══════════════════════════════ ════════════════════════════════╝ === Cut ===Wow! The Protoss are attacking my Zerlings! It's time to get going. Ivan. - Divorce the circuit, big and small.. [ Sprinter-II ] [ Forth-CPU ] [ ZX ]

Let your enemies, Eugene, die without sons! 1 May 2000 at 13:34, Eugene Stahov ═> All: ES> Before making a signet, I would like to listen to your thoughts ES> ALL knowledgeable about this issue. ES> To begin: ES> Basic properties, hardware features: ES> 1. MS-DOS file system hpfs... ES> 2. Ability to work with TR-DOS at level #3D13 (speed - high) high - what is it? ES> 3. Loading from a screw is possible how is it implemented? ES> 4. HDD port range: xx90h-xx9fh i.e. inir/otir not rolling? ES> 6. There is ms 62256-621024 (in the latter case you can disable the ROM ES> completely. ), in particular, this allows you to work with the screw in TR-DOS ES> (#3D13 emulation, sector buffering 512<->256) Is it supposed to be software caching of the screw sectors? ES> 7. Possible implementation in the future: ES> - second IDE port do you mean another controller on other ports? or now there is only master? ES> expected price < 10$ this is, of course, cool, although I ||. ES> QUESTION:ES> - what are the current IDE port layouts? smuc, by Jason, all under dos: ──{Begin} ───────────────────── ────────────────────── { ports .C } ── SMUC controllers ver 1.1 - 1.3 IDE registers. Command block registers. ┌───────┬──────────────────────── ───┬────────────────────────────┐ │ │ IN │ OUT │ ╞═══════╪════════════════════════ ═══╪════════════════════════════╡ │ #D8BE │ Data register D8-D15 │ Data register D8-D15 │ │ │ │ │ │ #F8BE │ Data register D0-D7 │ Data register D0-D7 │ │ #F9BE │ Error register │ Precompensation register (*)│ │ #FABE │ Sector Counter Register │ Sector Counter Register │ │ #FBBE │ Sector number register │ Sector number register │ │ #FCBE │ Cylinder number register │ Cylinder number register │ │ │ (low) │ (low) │ │ #FDBE │ Cylinder number register │ Cylinder number register │ │ │ (high) │ (high) │ │ #FEBE │ Drive/Head Register│ Drive/Head Register │ │ #FFBE │ Status register │ Command register │ ├───────┼──────────────────────── ───┼────────────────────────────┤Control block registers (block of control registers). Registers are available if bit 7 #FFBA is set. ├───────┼──────────────────────── ───┼────────────────────────────┤ │ #FEBE │ Alternate register │ Managing the state of the ac-│ │ │ states │ piter │ │ #FFBE │ Drive address register │ not used │ └───────┴──────────────────────── ───┴────────────────────────────┘ [censored] ──{End} ────────────────────── ─────────────────────── { ports .C } ── [WBR, Oleg. ] [ 01:31 7 May XXXV A.S. ]