Beta Disc Interface
ZXNet echo conference «hardware.zx»
Hello Lennon
The original and our clones were made on WD1793 (KR1819VG93 in my opinion)
The logic seems to be no different since TR-DOS would not work. The essence
controller is that when switching to 3Dxx addresses, disable the ROM on the board and
put yours there (with TR-DOS firmware) and in the case of 128 machines, turn it off
occurs only if ROM48 is enabled. When turning on the TR-DOS ROM
The VG93 ports and the BDI control/status port, in principle, all become available.
You will need to choose from the variant of your spec (48/128) also spec
expanded by replacing the 16K (32K) ROM with 64K and used BDI without ROM (NEMO BDI
like this)
Hello, All
This topic may have already been discussed, but I couldn't find anything. :v2_eek;
Eat; Google, etc., there are all sorts of WorldSpecial sites, etc. :v2_finge; ,; but I'm on
I couldn't find anything!
1. I need a BDI diagram so that everything can be seen normally, names, electrical
connections, elements, preferably one that is better in terms of work and spare parts.
2. Who can answer the question of how our BDI clones differed from the original? On
Which NGMD controller is the original made?
3. If anyone can sell a BDI that is not working, ... write here or in the PS
:v2_thumb:
Hello hero
her> You will need to choose from the variant of your spec (48/128)
I will have +3
There is just 64 kB of ROM, that is, nothing needs to be changed electrically.
Can I just flash the ROM and connect Nemo?
In general, the Pentagon had a 32 kb ROM, and 16 kb was just from tr-dos...
Am I right, can this also be done with +3?
Hello Lennon
>> In general, the Pentagon had a 32 kb ROM, and 16 kb was just from tr-dos...
Am I right, can this also be done with +3?
On the Pentagon 64k + 2k (1991 variant) the printer driver is flashed in the additional ROM if so
you can put it.
And at +3 you need to watch how the ROM banks click, besides, it seems like at +3 (maybe
I'm lying) the memory layout is switched and this is a matter of port 1FFD which is in
domestic software is very actively used, potentially because of this the software may
don't work
Hence the conclusion that you may have to disconnect port 1FFD (if there is one
finally possible) and redo the ROM switching in the spirit of TR-DOS
Hello Lennon
len> 1. I need a BDI diagram so that everything can be seen normally, names,
len> electrical connections, elements, preferably better in terms of
len> work and spare parts.
There is a publication of the diagram in the book “Do-It-Yourself Periphery”, Inforcom, 1994. It’s a pity,
that no one has yet made an electronic version of this publication...
len> 2. Who can answer the question of how our BDI clones differed from
len> original?
For example, there was a difference in the range of input addresses: 15616...15871 instead
15360...15615.
Hello Grand
Gra> There is a publication of the diagram in the book "Peripherals with your own hands", Inforcom,
Gra> 1994. It’s a pity that no one has yet made an electronic version of this
Gra> publications...
I'll look in the box, maybe I didn't throw it away, I had one like that
Hello, The Exploited
The> wow, I have just such clean boards
The> in the nth quantity
and how much is opium for the people?
Is it just a signet or an already debugged piece of hardware?
Hello, The Exploited
len> wow, I have just such clean boards
len> in the nth quantity
how much is opium for the people?
Hello, The Exploited
I have a question that I can't find the answer to...
As you know, entry into TRDOS occurs if you install the BASIC48 ROM (bit D4 7FFD
is 0) and read the command at addresses #3D00-#3DFF. In this case
the BDI trigger will work (install), the ROM will be replaced with TRDOS firmware and ports
FDC and FF will open for access.
Returning the BDI trigger to its original state (reset) is possible using the /RESET signal
or according to the second condition. This is actually the rub with the second condition. In general
In this case, the trigger will switch if it goes to RAM. But since TRDOS itself has
access to the RAM area (working with system variables, reading/writing data),
then it is logical to assume that not just circulation, but reading should take place
command code (/MREQ=0, /M1=0). Actually, this is how the formation scheme was constructed
trigger switching signal to Pentagon128. BUT, we can get a completely different picture
observe in NemoFDC - the trigger is reset by the WAIT signal (in KAY
CPU slowdown occurs when accessing only RAM) - indirect
sign of working with RAM...
Who thinks about this? How does it work?
Hello spensor
spe> In general, the trigger will switch if it accesses RAM. But
spe> since TRDOS itself has access to the RAM area (working with system ones
spe> variables, reading/writing data), then it is logical to assume that
spe> there should be not just access, but reading of the command code
spe> (/MREQ=0, /M1=0).
This is exactly how switching happens - by reading the command code, and not just by
treatment. You can read and write bytes in RAM just like that...
Hello spensor
spe> bit D4 7FFD is 0
1 after all. and in some computers by reset, and despite the fact that 7ffd also
is reset to zero, then we end up in the “hidden” 16k - shadow ROM (this is how it works in the pros)
spe> BUT, we can see a completely different picture in NemoFDC - reset
spe> trigger is carried out by the WAIT signal
this is clearly some kind of cunning idea by K. Hemo (the controller will not work anywhere except
his computers), and Maksagor wrote everything correctly
Hello, The Exploited
The> 1 after all. and in some computers by reset, and despite the fact that 7ffd
The> is also reset to zero, then we end up in the “hidden” 16k - shadow ROM
The> (for pros)
oops... I was wrong. Correct 0 - BASIC128, 1 - BASIC48.
The> this is clearly some kind of cunning idea by K. Hemo (the controller will not work
The> anywhere except his computers), and Maksagor wrote everything correctly
This is where everything is very interesting - there is nothing like that in the KAY scheme,
ordinary architecture. Moreover, I assembled NemoFDC on a breadboard and connected
to Leningrad-2, it worked great! But now I decided to figure out how, and
was dumbfounded. Nemo is definitely a high-class circuit designer!
Hello spensor
spe> But now I decided to figure out how, and I was dumbfounded. Nemo definitely
spe> highly qualified circuit engineer!
I would say combinatoric, considering what he called his creation - synchronous
state machine, he was clearly delighted with the scientific background of digital
circuit engineers. Here you go
Hello Lennon
A circuit designed as a state machine is more trustworthy than
developed "according to the rules of the Jedi Masters."
Hello, captain cobalt
cap> A circuit designed as a state machine causes more
cap> trust than developed “according to the rules of the Jedi Masters.”
Nevertheless, this “miracle of hostile technology” works, and works very well. And
I really want to understand HOW!? Maybe someone can make a guess?
Hello spensor
spe> Nevertheless, this “miracle of hostile technology” works, and it works very well
spe> good. And I really want to understand HOW!? Maybe someone will nominate
spe> guess?
look at the diagram CAREFULLY!!!
the tr-dos trigger is reset after TWO waits in a row not separated by an access
to ROM (CSROM) ! Should I tell you more or is it already clear :)
Hello Ronin
Ron> the tr-dos trigger is reset after TWO waits in a row not separated
Ron> by accessing the ROM (CSROM) ! should I tell you more or is it already clear
Well, I got to two WAITs myself, but beyond that it’s just not clear. If we
first read 2 (1 byte?) bytes of data, and then start executing commands
From RAM it would be clear. And so it’s not very good...
So please continue!
Hello spensor
The question is still relevant!
Hello Lennon
Then I will formulate the question more specifically. :)
Let's assume that TR-DOS transfers control to RAM without accessing RAM. In that
in the place where she transferred control, there is a one-byte command reading the ROM.
This one-byte command is read in one read. And therefore he will have time
read the contents of the TR-DOS ROM before it turns off.
Right?
Hello, captain cobalt
Damn, I’m running around here with graduate school, so I couldn’t immediately figure out the scheme correctly
rummage. Plus I didn’t have the diagram at hand :) but I looked it up yesterday. total:
1. Exit from dos is carried out using ONE wait (the second trigger is for NMI).
2. now we look at the KAY-256 (not turbo) diagram and we clearly see that wait happens ONLY
at M1/=0, i.e. only when sampling COP.
3. We take the KAY-256/1024turbo circuits and see a slightly more cunning circuit on KP12 and
TM8, but with the same result - with no turbo - wait only happens with M1.
4. we puzzle over the turbo mode and realize that turbo is disabled when dos is disabled
:)
Hello Ronin
Thanks for the comments and clarifications! True, one thing is not clear - I connected
homemade product for Leningrad2, everything worked. Or maybe there was something, but I wrote it off
on the incompatibility of L2 with the Pentagon...
PS; I'll double check; this may not be the end of the discussion.
Hello spensor
spe> True, one thing is not clear - I connected the homemade product to Leningrad2, that's all
spe> worked
so Leningrad also accurately generates white on M1
Hello, The Exploited
The> so Leningrad also accurately generates white for m1
I carefully reviewed the diagram (specifically Leningrad-2), it seems that
/M1 doesn't go anywhere from the processor at all...