Altera (Cyclone3?) or Xilinx (Virtex5?)
ZXNet echo conference «hardware.zx»
Hello, Vladimir Kladov
Vla> - I can’t figure out what the prices are.
If according to Altera then www.altera.ru
There you will find the price list for all available components.
Hello, Vladimir Kladov
I have such suspicions that you want to bring Spec256 to life ;)
IMHO - Altera DE1 is suitable for both teaching and experimentation
and for the final implementation.
ZY My religious fanaticism seems to be more towards Altera :D
Hello icebear
Yes, there are prices on Altera, I was confused, including in terms of which is better
choose that there is no such certainty about xilinx (plis.ru). "Price
getting ready" - the sign has probably been hanging since the beginning of the year.
I have already chosen the language (verilog, of course, I have no brain for complex constructions
is no longer enough). The software, however, has not yet arrived - I myself can’t download it via dial-up
I take it, a lot. I asked, they will do it. I'm still struggling with Max+ 2 something.
(the interface is clearly from 1996, judging by the dialogues and the terrible text editor)
and the crooked Veritac. Well, I’ve made an emulator for the PC so far, check what
percent will generally work (and there will be enough commands for all), we have to do it somehow.
Books are hard. I thought I’d find something on the counter, but it’s generally complete
bummer. What I found on the Internet will not be enough. Okay, I'll figure it out
somehow. I’ll go to a top book this week, I’ll be scared by the prices there.
Maybe I’ll find a newer tome within 1000 wooden ones.
Wait a while with the board... Really, what's the rush? I might need a year
complete the project, and then lo and behold, newer and cheaper chips will fit, and
boards for them... Thanks for the advice.
Hello, Vladimir Kladov
no, Z80 is the 20th century and all x86s and RISCs... I have a completely different architecture
formed in my head. And there are a lot of ideas for parallelization, or rather for
asynchronous execution of instructions (not in the asynchronous sense that there is
in mind when programming FPGAs, for simplicity I am going to do everything
synchronous. It's just that an instruction that came later can begin to be executed
earlier or simultaneously with those who arrived earlier - as the operands are ready). B
In general, this is not speckrum at all, not risk, not x86. And the main idea is memory protection
accurate to 4 bytes, + complete isolation of both stacks - computational and
returns/exceptions. The program will not have access to them as memory. Like this.
Hello, Vladimir Kladov
Here you need to have a fairly deep knowledge of the architecture of state machines and
decomposition of operational and control blocks, in short, from the beginning
build a mathematical model so that all the shortcomings surface as in the language
where all commands are executed in parallel it is pointless
Hello, Vladimir Kladov
Vla> this is not speckrum at all, not risk, not x86. And the main idea is protection
Vla> memory with an accuracy of 4 bytes, + complete isolation of both stacks -
Vla> computational and returns/exceptions
Fort processor?
Hello Lethargeek
not really a fort. I only take the principle of stacks from him. Another principle
“everything is available to a programmer” I completely reject. Everything is available in x86 too. Yes so
it is accessible that there is nowhere else to go.
I made a model. We know how to write emulators :). I have a good parallel
thinking at the level of intuition. Build a mat. model - no longer needed, its better
keep it in mind, it’s easier to immediately model it in verilog. Actually I don't
circuit designer But once upon a time I had the good fortune to get acquainted with the basics. What is
RS trigger or inverter, I imagine. With large logic such as registers or
The more I can figure out the adders. My problems start when it happens
reaches the soldering iron and solder. But I don’t set myself such a task. Moreover
that now (it turns out) you can do iron training while being full of iron
lamer (in the sense of running this thing on a test board from the manufacturer, in
real hardware, without even being able to correctly count the legs of a microcircuit :)).
Hello, Vladimir Kladov
Interesting things are written about Lattice FPGA. Fast, inexpensive, and memory 5 times greater
more on board. I was especially pleased with the support for DDR SDRAM on board. Narld,
do you use it? Or, once you’ve become imbued with an alter, you don’t look around?
Hello hero
her> Any more or less modern FPGA has DDR SDRAM
her> take the crust and that’s where the actions end
her> and for Lattice programmers cost crazy money
Oh, well, it’s expensive for piece production. And for large-scale production
Actually, I don't care. Okay, as soon as I switch to large-scale production, I will definitely
I remember :v2_wink2:
Hello, Vladimir Kladov
Any more or less modern FPGA has DDR SDRAM
take the crust and that's the end of the action
and for Lattice programmers cost crazy money
Hello, Vladimir Kladov
Vla> I don’t know what to choose. Firstly, which company is better to start with.
Vla> For reasons of convenience, I would like a development tool. Which is better -
Vla> Quartus alter or ISE xylinx?
I may not discover America, but I think in this case the resource will be useful
http://iosifk.narod.ru/articles.html
There are several articles about creating a fort-like microprocessor "with your own
hands" in FPGA. Articles were published in the journal "Components and Technologies",
posted on their author's page.
As an example, a project based on Altera, the AlteraHDL language, and the package
MaxPlus. The author of the articles considers AlteraHDL more accessible, and the transition from it to
other languages are simpler.
Vla> Secret from the processor device (no name yet, just made up
Vla> names are hard) I don’t do it. I update the description regularly
In my opinion, for the initial project the architecture is “overweight” with innovations and
bells and whistles like the presence of hardware floating point calculations in it.
It seems to me that it would be more promising to pay attention to massive parallelism
in an array of simpler nodes, with a very large number of them (nodes).
http://www.lenta.ru/news/2006/11/07/multicore/
I had ideas of trying to experiment with these in a simulator. Costack language like fort on a node scale and in perspective with an explicit language
Occam-type parallelism for the system.
Unfortunately, things didn’t go further than ideas. :v2_down:
Hello Jenner
I've read it a long time ago. There is AHDL, which is time to retire. Somehow it’s clear, but to me
I didn’t like it, I prefer verilog.
Real - optional. Naturally, it won’t be in younger models. I
I’ll probably start with a 16-bit data model (but the addresses are 32). I'm not very
It’s interesting to make even a simple conveyor. I want to do it asynchronously
execution, BESM-6 principle (water supply != conveyor!). No, I don’t want an array. I love you
classics. (You yourself reproach that there are too many innovations. Massive computing
- this is such an innovation for me that the only innovations further are quantum ones
calculations...)
Hello, Vladimir Kladov
As I understand it, it’s just an ancient development (wow, time flies - 5 years, it’s already ancient!).
Back then the chips were smaller and slower. And now - Lattice - 800MHz, inside PCI,
Ethernet, flash for firmware, and whatnot. The Pentium just didn't
Enough to do... And even enough - in a stripped-down form, but there’s no need for it. For
Sucks and a dump of rubbish!
Hello, Vladimir Kladov
Vla> And now - Lattice - 800MHz
This is the trigger switching time if you have 2 sequential operating frequencies
400 MHz and if there are a couple more LUTs, the differences between their synchronization inputs +
delays of the tracing resource, then we can hope for a maximum of 300, let’s say then
MAX3128-10 operating frequency of the macrocell is 100 MHz (even more than 175), then let’s say
in ULA for 64 Macrocells, the operating frequency of the maximum current chain is 9 MHz (the highest
the far corner turned out - the formation of the FLASH signal), but since those nodes where
nada 14 MHz work at 14 safely (taking into account all the latches, counters and
multiplexers) and FLASH if it is delayed by half a clock cycle is not scary, then
we can say that the circuit operates stably at 14 MHz
Here's an even more brutal example:
EP2C5, whose macrocells easily operate at 380 MHz - I stuck an ARM7 in there
kernel as a result after calculating all latencies (optimization was set to
size) ARM operating frequency turned out to be just under 3 MHz, and this is one of the most
linear processors
Hello, Vladimir Kladov
For me, AHDL is finally not a language for describing hardware, but a text representation
circuits, nothing seriously can be implemented on it
Hello, Vladimir Kladov
A bit off topic and excuse me, I have an Altera EPX740LC68-10Z. What kind of miracle is this?
Hello hero
what does 2 consecutive mean? Am I a fool or what, sequential triggers
connect? The trigger must switch once per clock cycle, and that’s it. That's why, my friend,
the conveyor exists. Now I’m just making, I think, a conveyor for the allocation queue
numbers for free "hangers in the wardrobe" (narrow resource - operating rooms
cells, 8 of them must be given to the command conveyor at each clock cycle, and
accordingly, take from those who no longer need it). It turns out 5 stages
conveyor, but the work of 8 cloakroom attendants at the same time is guaranteed, on each
Up to 8 coats were issued, up to 8 coats were accepted. (One bad thing - I can’t imagine
for now, how many lutes and valves it will be - for 128 numbers, for example, there
32 muxa mixers for 4 inputs on the lower stage, 32 muxa mixers on 2m, then 8 + 8
approximately according to the same scheme, but there are still return lines for re-liberation
unaccepted coats, and the 7-bit numbers themselves must be pushed on the tires
forward...).
ARM7 is actually G. There the conveyor skips stages and works smoothly
sequentially. Each clock cycle can only be executed by 4 different ones at the same time
conveyor stages. I want to make it run from 4 to 16 commands
simultaneously, and in average mode, 4 operations were performed per clock cycle. The conveyor is very
long, and with asynchronous execution of operations: a command that comes later can
finish your business earlier, dependencies are determined automatically. For this IRemoved the very concept of checkboxes. Okay, did I give you a link? Gave. I want to sleep...
I trusted for the day.
Hello, Vladimir Kladov
Well, I mean that the conveyor is the only way to increase
frequencies, the higher the signal chain, the naturally higher the frequency. But
Long conveyor belts, you think, and without me you know, there are also disadvantages.
PS: I’m very strong about user-controlled (compiler) parallelism
E2K reminded Babayan, you probably can’t think of a simpler way to resolve
data communications and the possibility of parallel execution of commands.
Hello, Vladimir Kladov
I know. I'm waiting for the disc to arrive. While I looked at the protel. VHDL, although the one who gave it,
said that Verilog. However, I already suspected that something was wrong: he doesn’t know
differences between Verilog HDL and VHDL.
Does ActiveHDL translate to C/Delphi?
Hello, Vladimir Kladov
Vla> Does ActiveHDL translate to C/Delphi?
No, you write it yourself (although there is a rather interesting SystemC event, like it
have already been brought to the point of being synthesized) but this is when the project becomes sufficient
big, let’s say when you have one processor cycle and it will be simulated for 2 minutes
then there will be nothing else left, and the native FPGA does not have such ease of debugging
as in environments when after fixing == to != there is no need to recompile the entire project
and re-upload it to the debugging kit.
Hello, Vladimir Kladov
If you want a convenient writing environment and the fastest process simulation, then
you need Active-HDL, but if you seriously want to simulate it as quickly as possible then
you can transfer fully debugged blocks to C (or possible to Delphi) and
connect them as PLI and using testbenches you can compare their behavior
Hello hero
her> No, you write it yourself (although there is a rather interesting SystemC event,
her> It seems that it has already been brought to the point of being synthesized) but this is already when the project
her> becomes quite large, say when you have one bar
her> the processor will be simulated for 2 minutes, then nothing else
her> will remain, but the native FPGA does not have the same debugging convenience as in
her> environments when after fixing == to != there is no need to recompile the whole
her> project and re-upload it to the debug kit.
I can’t imagine what it’s like myself. I can make a logical emulator myself (actually
already). There is icarus verilog - it can automatically create a C-model. But with him
It’s inconvenient to work with: command line, I don’t really like it. But if the need arises, I’ll be there
use.
Hello, Vladimir Kladov
Vla> I will have many different conveyors (I’ve already counted 6), and from them
Vla> only 1 - instruction pipeline, may cause suspension due to
Vla> transitions (and the rest click without a break, if there is something to do
Vla> work).
Of course, it's probably interesting to create your own processor, but it's interesting
What is fundamentally supposed to be new in it? Conveyors of all stripes and types
have been used everywhere for a long time. Moreover, from automatic (at the Dispatch level
Unit) out-of-order command execution in new processors begins to fail,
shifting this task partially to compilers, which compilers cope with
much better than it would have been done on the fly. An example would be
the same new Cell processor from PS3.
Hello Titus
I told you what's new. Memory protection up to 4 bytes. Also, I'm interested in
put everything you need into one chip: video, sound, interfaces, and make the most
cheapest, smallest and most reliable celeron class computer (i.e. also
the fastest of the classical soft processors). And then, I go on and on,
Taldychu: I DO NOT HAVE A CONVEYOR, I HAVE A WATER PIPELINE.
I've already heard about CELL. It was not possible to adapt Linux for it in a normal way.
The coprocessors remained unused, all 8. Only the main one works. This
called: compilers "cope". Writing a good compiler now
more expensive than developing hardware that optimizes the program on the fly.
How many languages are there in the world, do you know? For everyone to write optimized compilers -
How many programmers do you need? There aren't that many of them...
Hello, Vladimir Kladov
Vla> I told you what’s new. Memory protection up to 4 bytes. Besides me
Vla> is interested in putting everything you need into one chip: video, sound,
Vla> interfaces, and make the cheapest, smallest and most reliable
Vla> celeron class computer (i.e. also the fastest of the soft processors
Vla> classical type). And then, I go on and on: I DO NOT HAVE A CONVEYOR,
Vla> and WATER PIPELINE.
Almost a utopian task)))
Not to mention the fact that if it remains in the FPGA, then it is unlikely that it will
cheap. And to make fun of production in silicon... this is generally UNREAL
I also don’t understand how a water pipe differs from a conveyor (according to the description
purely a conveyor ;-)). And therefore the performance is standard for systems
this type.
Hello, Vladimir Kladov
What's the point of 4 bytes of protection?
It seems like 4Kb is quite a convenient value, anyway, there is no severe fragmentation right now.
It would be more interesting to have hardware heap management and out-of-bounds control
dedicated area, such as goodbye holes associated with buffer overflow, and also
it would be more fun to include in the descriptor of the selected area in addition to the address and size
a data type was also stored, such that the processor would drop out in Trap when not
(designed in a special way) access to the cell in which it is stored
pointer as to a real number. It would also be useful for operating systems in
this descriptor stores the sign of modification, and the sign falls into
debugging with a certain type of access.
PS: Oh, we’re offtopic too :)
Hello hero
The point is that programs written with errors and accessing the WRONG WHERE
within OWN heap, they fell immediately, even from the programmer, and not from the user. What if
fell on the user, so that it was visible not the place where the program “hit”, but
the place _from_ where she got there. And no more buffer overflows. And if in
within 4K, then it won’t give anything, just as it doesn’t give anything now.
Hardware heap management is exactly what I provide. I believe that
many programs slow down precisely on this. But to confuse real and
whole - just let the translator figure it out. If the language is normal, there
There are no such problems (almost none). This is in C - you're always welcome. Well, don't write like that
on S.
A pipeline is when all commands go through the same stages of execution.
Let's say 6 or 8 or even 20. If some team does not need the stage, it
lets her through. If one is delayed, the entire conveyor is held back.
Plumbing is when each team works independently (as much as possible).
In the water supply it may happen that the one who comes later will do her business earlier
(if it does not depend on the previous ones). I have a problem identifying dependencies
can be solved in hardware and in very simple ways.
Utopian, of course. But sometimes it happens, a miracle happens...
Hello, Vladimir Kladov
Vla> In the water supply it may happen that someone who comes later will do her own
Vla> things to do before
Intel has implemented this starting with the Pentium Pro, it’s called out of order
execution. The usual pipeline is used, plus register renaming
(several hidden register files) and several modules with ALU and
branch prediction.
A protection granularity of 4 bytes will result in half of the memory being
occupy a block attribute table (RWX or something similar). Not for nothing on new ones
processors (starting from Pentium) made support for 2MB and 4MB pages (in order to
so that the page table takes up as little memory as possible).
Hello, Vladimir Kladov
Vla> where the program “got”, and the place _from_ where it got there
Well, this problem can be solved in an elementary way (either a stack trace for call, or
FIFO transitions as done in DSP TMS320VC5502 for debugging purposes (remembered
about 20-30 transitions and cycles)).
Hello, Vladimir Kladov
Vla> A pipeline is when all teams go through the same stages
Vla> execution. Let's say 6 or 8 or even 20. If some team has a stage
Vla> is not needed, it skips it. If some are delayed,
Vla> adheres to the entire pipeline. Plumbing is when each team
Vla> works independently (as much as possible). In the water supply it may
Vla> it may happen that the one who comes later will do her business earlier (if not
Vla> depends on the previous ones). I have a problem identifying the dependency
Vla> is solved in hardware, and in very simple ways...
What you call a water pipeline is an ordinary conveyor that has been in use for a long time
:-) And out-of-order execution of commands is its usual feature :-)
Hello Titus
Tit> water supply
water supply in English - pipe and conveyor also in English pipe
Hello, Vladimir Kladov
Vla> I just don’t understand, but what does all these MSRs have to do with it? What's the use of them - if
Vla> is just a means of obtaining information about the capabilities of the equipment
Read the original source (Intel processor manual volume 3 (from the Intel website)),
and not a Russian translation by someone unknown. In the MSR register area there is an area of
16-32 registers that remember the last 16-32 transitions (all types
transitions call/jmp/int, etc.), you can’t just use it,
because the Page Fault exception handler must first save
the values of these registers (otherwise transitions that
occur inside the handler).
Well, regarding 100,000 lines of code, I can only say one thing: on the computer the code
debugging is much easier than, for example, in an embedded system on TMS (which has
there is no memory protection at all) and besides the JTAG emulator there are no means of communicating with
the outside world (no monitor or keyboard).
I am developing kernel mode drivers (for systems based on the NT kernel) and source code there
about 1MB, but this doesn’t stop me from finding and correcting errors. Most
errors can be corrected based on purely theoretical principles. The rest with
using control code (asserts) and all sorts of debuggers and tools like
checker bounds.It is clear that it is very difficult to write code without errors, but for this purpose
There are all sorts of different debugging techniques to correct errors, including
elusive.
Hello, Vladimir Kladov
Vla> Kolya already, otherwise my situation with the program turned out exactly like this -
Vla> had to postpone the project for a long time
There's DevPartner Studio (formerly BoundsChecker) for this.
Hello, Vladimir Kladov
Vla> Memory - exactly 2 times more is needed.
Well, this is wildly not optimal. It's like Bill Gates promoting his everywhere
BASIC and C# (although these are wildly slow and a huge waste of memory, in
As a result, any computer runs at 386 speed). Remember algorithms
from Knuth's books (everything there was optimal and written in assembler).
Hello, Vladimir Kladov
Vla> multi-threaded task (> 5 threads)
Moreover, DevPartner allows you to detect deathlocks in multi-threaded programs,
and does it quite effectively.
Hello, Vladimir Kladov
Vla> this is a paid thing
Well, free - just cheese in a mousetrap. Delphi is also a paid product. And anyone
software for development for alter - too (and costs a lot of money).
Hello, Vladimir Kladov
Vla> this is a paid thing. And I tried it. She can't do anything. In this
Vla> situation - nothing. I don’t know where she is, what I need to tell her so that she
Vla> indicated where the legs grew from. Yes, I forgot to say: the task is multi-threaded
Vla> (> 5 threads), and it’s generally unclear in which thread the crash occurred.
In order for all checks to work, you need to compile with its library (for MSVC)
older versions also supported Delphi, there was BoundChecker Delphi edition. At the same time
Errors are caught up to a specified number of bytes. The technology is very simple,
before calling the function, the arrays and stack are filled with a pattern, then this pattern
it is checked, if there were overflows - this is immediately detected.
The problem, as always, is not in the hardware, but in crooked programmers, what a good thing
don’t make hardware and there will be those who will write a program that will work
with glitches on the most fault-tolerant hardware. People used to program on ASMA
and identified all the errors, but now they cannot identify errors in the nuclear power plant (although this is on
the order is simpler).
Mostly the presence of difficult-to-debug errors in the program,
determined by programming style. I have one domestic book
(back in the 60s), called “Individual debugging of programs”, there’s about it
very well written. The book is still relevant today.
Hello, Vladimir Kladov
Vla> is this in the PC?
Yes, it is in all processors starting from the Pentium Pro (see Intel's document on the process
3)
Hello deathsoft
dea> Use MSR registers that have trace fifo as in TMS (at 8
dea> or 16 transitions depending on the processor model)
Where can I get this? Is it available at the PC? How to use it? If you have already, otherwise I have
The situation with the program turned out exactly like this - I had to postpone the project for a long time (no,
not EmuZWin, everything is fine with him, just no time).
If about this:
Model-Specific Registers Model-specific registers.
These registers provide a means of software communication with the microarchitecture
processor, all the most important settings that can be changed programmatically are located
right there.
RDMSR and WRMSR Commands
The RDMSR (ReaD from Model Specific Register) command reads from
MSR register. The command's action is to check two conditions: first,
the presence of a zero privilege level of the code is checked, secondly,
the presence in the ECX register of a value that addresses one of the MSR registers is checked.
If at least one of these conditions is not met, then executing the RDMSR command
ends. If both conditions are met, then the value of the MSR register,
addressed by the contents of the ECX register, placed in a pair of 32-bit registers
EDX:EAX.
then this is unlikely to help.
Hello deathsoft
Yes, of course, not optimal. Storing boolean in a byte is also not optimal. You know,
What is actually NOT OPTIMAL? It is not optimal to not be able to find
maximum errors in the program before it freezes and freezes the system. Not
optimally - force programmers to look for bugs that could manifest themselves
themselves, and say - “here is a mistake.” It’s not optimal to try to make a non-holey one
the axis is on iron that is leaky by definition (see the Singularity project).
Hello deathsoft
The project is in Pascal, but who cares. The pattern method does not work. Checked and
other means that fill everything with a pattern. (I just don’t understand, but when
Why are there all sorts of MSRs? What's the use of them - if it's just a means to get
information about the capabilities of the equipment). There is a very deep, induced error there. And
probably not even mine, but in one of the graphics libraries. Crooked programmers
you say? You try to write 100,000 stock codes without errors, but I
I'll take a look. A good mistake is one that immediately leads to a failure. But there are bad ones
errors. The function works fine, nothing happens. At first glance,
both on the second and on the tenth. But somewhere in memory it does something wrong. And later
minutes of long execution, another function elsewhere starts calling
data, but they are somehow not the same. It is impossible to foresee all cases, and the program with
falls with a roar. Now try to guess which of the 10,000 functions is not something
takes into account. These are not crooked hands of programmers. This is lazy hardware + principle
"everything is available to the programmer." I believe that software development now requires
pour in more and more money and time and effort - just because there is too much
savings on hardware development. "We won't make a steam locomotive, here's 100
horses, ride wherever you want." That's how it works.
Hello deathsoft
what table... There is no table. Just imagine - 4 bytes at the address
0000_0104H. And “under” them there are 4 bytes of descriptor, at address 1_0000_0104H. On
in fact, shadow memory with descriptors can be addressed so that
SDRAM both four are included in the same line. And there might be a group handle on
256 bytes. And I think that's enough. Memory - exactly 2 times more is needed. But
It will be easier for programmers to live - now this resource is more expensive than some kind of memory.
Hello deathsoft
this is a paid thing. And I tried it. She can't do anything. In this situation -
nothing. I don’t know where there is, what to say to her, I need her to point out where her legs are from.
grew up. Yes, I forgot to say: the task is multi-threaded (> 5 threads), and in general
It is not clear in which flow the flight took off.
Hello, Vladimir Kladov
Vla> Well, what does an ordinary developer (not kernel level) need from these registers
Vla> if he can use them.
So this is not a hardware problem, but a problem of crooked tools that
do not support the equipment they work on. The same SoftIce debugger
supported MSR registers, but only LastBranchFromIp and LastBranchToIp.
Hello, Vladimir Kladov
Vla> The stack is always available to the program as an addressable space. In the same
Vla> the stack itself contains return addresses, local variables, and
Vla> parameters. The pattern method will not help here.
Well, in general, the method of patterns with a stack helps a lot, the stack is checked
after each function call, uninitialized
variables and stack overlay on the code.
New x86s have a page protection bit that allows/disables execution
code from this page, the attributes are set to RW for the stack, for data also RW, for
RX code, while writing to the pages with the code immediately leads to an exception, and
also attempt to execute data and stack.
By the way, on x86 it is possible to protect the stack, code and data, almost like in
computers with Harvard architecture - this is the use of a segment model,
when each segment is given its address and size, then when there is overflow
stack, a Stack Fault exception is thrown. Nobody uses this because
that writing a compiler for the segment model is 100 times more difficult, so everywhere
use a simplified FLAT model. In its test multitasking OS, which
I wrote in assembler, I used segment level protection and all 3 rings
protection (just to see what advantages this gives),error protection increases significantly, but compilers that support this
no, and of the OS only OS/2 supported privilege levels 0, 2 and 3, all others
The OS only supports 0 and 3.
Hello, Vladimir Kladov
Well, I received Quartus II 6.1. I haven’t figured out yet whether it will come with a Web license
Edition, I'll try it now.
Yeah, it seems to be going well. expiration date; 27-Jun-2007.; For six months, that is. Via
They will give you a new one for six months if you ask on behalf of the same network card / user,
who knows, tell me.
I'll go and look through the tutorial ;)
Hello deathsoft
Well, what does an ordinary developer (not at the kernel level) need from these registers, if he
can use them. Mistakes are mistakes, but there are also intentional ones
malicious code that you can’t run or hide from on x86. Stack program
always available as addressable space. In the same stack are also
return addresses, and local variables, and parameters. The pattern method is not here
will help. In addition to natural errors, it becomes possible to find a rare case
combination of input data and a buffer overflow to execute code that never
should not have been executed in the normal case. Architecture in which
stacks are separated and not addressed like regular memory, eliminating such
opportunity completely.
Hello deathsoft
Total stack? In every thread? Well, you touch me. I say: until
If an error occurs, you will have to run the program for several days then.
After the call, you will have to check all the memory belonging to the task. That's what I mean
I tell you that this is unrealistic.
And then, imagine an ideal world. The program can be written immediately so that
if an error occurs within a protected block, the program will not crash, but
it will simply report that this piece of data is faulty and skip it, and then
will do. Or maybe not report it, just record it in the journal - if the task
like this. And now - please see that "the program performed an unacceptable
operation,” and half an hour of your previous expectations were covered with a copper basin. And be
kindly use the method of elimination (for example) to find the piece of data that drops
program, and remove them from the set. The example is abstract, but characterizes the current
the state of affairs is complete. The developers don't even try to provide
recovery from a crash, because a crash will definitely ruin the shared heap,
accessible to the entire program with unified rights, and continue to try to execute
anything is simply meaningless: recovery is impossible.
No, of course, you can organize your own for each small task
process (fallen - the master process restarts the slave), but - expensive
It turns out that it will slow down, and slow down a lot.
Hello, Vladimir Kladov
They give it, although it’s easier to cure, the debugger in qartus is poor, one might say it’s not there.
Hello, Vladimir Kladov
Vla> No, of course, you can organize your own for each small task
Vla> own process (fallen - the master process restarts the slave),
Vla> but it turns out to be expensive, it will slow down, and slow down a lot.
Well, you don’t have to go far, an OS with a mach kernel (microkernel OS, where all the processes and
drivers work in usermode). There all processes can be restored. Exactly
also most military applications, there is almost always a requirement
passing the program checkpoints and recovery in case of failure from these
control points.
Hello, Vladimir Kladov
Vla> I'm telling you: before an error occurs, you will have to run the program on
Vla> a few days then.
You can make the granularity of memory protection at least 1 byte, but if the program spoils
someone else's memory that is writable, then this will not help at all. (For example 5
functions use one structure on the heap, and one of the functions writes there
garbage). The PROGRAMMER is responsible for the correct operation of the program and nothing more.
Hardware is only a tool, otherwise there would be no programmers at all.
are not needed, computers would write and debug programs themselves (as in scientific
fantasy novels).
Hello deathsoft
And also, for example, I have developed a rule for myself - do not use
projects libraries and components (vcl/mfc, etc.) that do not have source codes (not
it is important whether it is a commercial library or not), because in glitch libraries
there is plenty, and when there are no sources, it is impossible to fix glitches. I found and
I fixed more than one glitch in controls and libraries for C++ Builder.
Hello deathsoft
dea> The PROGRAMMER is responsible for the correct operation of the program and only
+1
By the way, the same Fort very simply allows you to brutally redefine everything that is possible
so much so that the programmer will become "UNAVAILABLE" everything. :) Of course the brakes
arise, but for the test version that’s it. IMHO normal usage control
Hardware resources are much more important than memory protection.
Hello, Vladimir Kladov
Vla> Jpeg, Jpeg2K
Intel has it
(http://www.intel.com/cd/software/products/asmo-na/eng/perflib/ipp/302910.htm)
with optimization for the latest processors.
This library also includes mpg-2, mpeg-4, H.263, H.264 encoders/decoders.
Hello, Vladimir Kladov
Vla> Web Edition breaks down with the choice of chip, infection
I can give you a link to the full edition (although there will be 700-800MB from ftp
download) and send the medicine in a personal message.
Hello, Vladimir Kladov
Vla> I didn’t understand what 61_quartus_programmer.exe (50 meters) is.
This is not needed, this is a separate programmer so that there is no quartus in the microcircuits
upload ready-made firmware. The programmer goes inside the quartus.
Hello, Vladimir Kladov
Vla> Can someone quickly tell me how to do something like this in the `for loop
Vla> shove (if this is even possible)
The Verilog 2001 standard for loops and conditionals is sufficient, but in general I
I would advise using VHDL (it is similar to Pascal and Ada, I think this is for you
will be more familiar) and supports if/generate and for/generate from the very first
versions. Plus it supports data types like a regular language
programming, which allows you to see the state when modeling the machine
machine in the form of meaningful text (s_idle, s_rx, etc.). Also VHDL
supports 9-digit logic, except for '0' states
Hello, Vladimir Kladov
Vla> I especially liked the concatenation in { }.
Well, this is how concatenation is done in VHDL;
e1<=e(1; to 4) & e(12+1 to 12+4) & e(2*12+1 to 2*12+4) & e(3*12+1 to
3*12+4)...
e1 - 96-bit vector;
Hello, Vladimir Kladov
Vla> The saddest thing is that there is no normal description of the algorithm
Most likely it exists, but this standard is simply paid, or proprietary and
distributed under NDA.
Hello, Vladimir Kladov
Vla> There is a two-dimensional array
Why can’t you write nested loops in a regular System? I'm just 100 years old
I didn’t write anything in the verilog, because... in the simulation there are only 0 and 1, then I switched to VHDL.
Hello, Vladimir Kladov
Vla> This is not closer to Pascal, but to COBOL
Unfortunately, I don’t know Cobol (I don’t even know what the syntax looks like).
But the syntax of VHDL is similar to that of the ADA language; all parallel actions are described in
form of processes.
P.S. Perhaps Cobol also has a similar syntax.
Hello, Vladimir Kladov
Vla> I just still haven’t received the textbook by mail
I can send you the IEEE standard for Verilog, all the syntax is described there, and a book
according to verilog from Cadence (although there is verilog 98 without for generate).
Hello, Vladimir Kladov
Vla> everyone unanimously affirms that it is C
So in verilog all operations are ss >>,<<,|,&, etc. And VHDL needs declarations
ala interface/implenentation, types are described in Pascal style:
x:integer;
v:std_logic(3 downto 0);
The operations are also Pascal: or, xor, and
Pascal cycles:
for i=0 to 10 do
begin
end
Hello, Vladimir Kladov
Vla> e, quartus stumbled on the declaration of a two-dimensional array
So this is an incomplete implementation of verilog in quartus, use something like
Synplify Pro or Leonardo Spectrum, and upload only the result of these to the quartus
programs (RTL level, only registers, logic elements and wires).
Hello, Vladimir Kladov
Vla> of our Soviet three-address machines
Well, three-addressing wasn’t invented here either (BESM4 and NAIRI are just
domestic implementation of a three-address machine), the same MIX whip - three-address.
Hello, Vladimir Kladov
Vla> that on verilog the text is much shorter
I also liked this Verilog, at first I wrote everything in Verilog, in VHDL
moved solely due to the lack of for generate in verilog (in the then
version) and because of the oak simulation with binary signals. And for synthesis verilog
more convenient (this is actually why it was developed and used by Cadence).
Hello deathsoft
By the way, the topic is named incorrectly - there is no cyclin 3 chip, apparently it was meant
Stratix III (since there is a comparison with Virtex 5, and these are circuits of the same level), and
Cyclon matches Spartan.
Hello, Vladimir Kladov
Ok, I just downloaded some System Verilog doc, I don’t need the 2001 standard
they'll grab it. Can someone quickly tell me how to fit something like this into a `for loop?
(if at all possible):
┌─- CODE ───
module OperRegQueue_step1(clk, reset, in_free_flgs, in_empty_triads,
out_reset_flgs, out_nums, out_write);
input clk, reset;
input [63:0] in_free_flgs;
input [2:0] in_empty_triads [15:0];
output [63:0] out_reset_flgs;
output [5:0] out_nums [2:0] [15:0];
output [2:0] out_write [15:0];
reg [63:0] free_flags;
OperRegQueue_mux1 mux0( clk, in_free_flgs[3:0], 4'd0, in_empty_triads[0],
out_write[0], out_nums[0][0], out_nums[1][0], out_nums[2][0],
out_reset_flgs[3:0] );
OperRegQueue_mux1 mux1( clk, in_free_flgs[7:4], 4'd1, in_empty_triads[1],
out_write[1], out_nums[0][1], out_nums[1][1], out_nums[2][1],
out_reset_flgs[7:4] );
OperRegQueue_mux1 mux2( clk, in_free_flgs[11:8], 4'd2, in_empty_triads[2],
out_write[2], out_nums[0][2], out_nums[1][2], out_nums[2][2],
out_reset_flgs[11:8] );
OperRegQueue_mux1 mux3( clk, in_free_flgs[15:12], 4'd3, in_empty_triads[3],
out_write[3], out_nums[0][3], out_nums[1][3], out_nums[2][3],
out_reset_flgs[15:12] );
OperRegQueue_mux1 mux4( clk, in_free_flgs[19:16], 4'd4, in_empty_triads[4],
out_write[4], out_nums[0][4], out_nums[1][4], out_nums[2][4],
out_reset_flgs[19:16] );OperRegQueue_mux1 mux5( clk, in_free_flgs[23:20], 4'd5, in_empty_triads[5],
out_write[5], out_nums[0][5], out_nums[1][5], out_nums[2][5],
out_reset_flgs[23:20] );
OperRegQueue_mux1 mux6( clk, in_free_flgs[27:24], 4'd6, in_empty_triads[6],
out_write[6], out_nums[0][6], out_nums[1][6], out_nums[2][6],
out_reset_flgs[27:24] );
OperRegQueue_mux1 mux7( clk, in_free_flgs[31:28], 4'd7, in_empty_triads[7],
out_write[7], out_nums[0][7], out_nums[1][7], out_nums[2][7],
out_reset_flgs[31:28] );
OperRegQueue_mux1 mux8( clk, in_free_flgs[35:32], 4'd8, in_empty_triads[8],
out_write[8], out_nums[0][8], out_nums[1][8], out_nums[2][8],
out_reset_flgs[35:32] );
OperRegQueue_mux1 mux9( clk, in_free_flgs[39:36], 4'd9, in_empty_triads[9],
out_write[9], out_nums[0][9], out_nums[1][9], out_nums[2][9],
out_reset_flgs[39:36] );
OperRegQueue_mux1 mux10( clk, in_free_flgs[43:40], 4'd10, in_empty_triads[10],
out_write[10], out_nums[0][10], out_nums[1][10], out_nums[2][10],
out_reset_flgs[43:40] );
OperRegQueue_mux1 mux11( clk, in_free_flgs[47:44], 4'd11, in_empty_triads[11],
out_write[11], out_nums[0][11], out_nums[1][11], out_nums[2][11],
out_reset_flgs[47:44] );
OperRegQueue_mux1 mux12( clk, in_free_flgs[51:48], 4'd12, in_empty_triads[12],
out_write[12], out_nums[0][12], out_nums[1][12], out_nums[2][12],
out_reset_flgs[51:48] );
OperRegQueue_mux1 mux13( clk, in_free_flgs[55:52], 4'd13, in_empty_triads[13],
out_write[13], out_nums[0][13], out_nums[1][13], out_nums[2][13],
out_reset_flgs[55:52] );
OperRegQueue_mux1 mux14( clk, in_free_flgs[59:56], 4'd14, in_empty_triads[14],
out_write[14], out_nums[0][14], out_nums[1][14], out_nums[2][14],
out_reset_flgs[59:56] );
OperRegQueue_mux1 mux15( clk, in_free_flgs[63:60], 4'd15, in_empty_triads[15],
out_write[15], out_nums[0][15], out_nums[1][15], out_nums[2][15],
out_reset_flgs[63:60] );
always @(posedge clk)
if (reset)
begin
free_flags = 64'b0;
end
else
begin
free_flags = free_flags & in_free_flgs | out_reset_flgs;
end
endmodule
└── CODE ───
It will take me so long to draw all these module calls, if without `for, and
I'm afraid there will be more errors.
Hello deathsoft
No, Quartus stumbled on the declaration of a two-dimensional array, I had to choose
set System.
But I don’t write in Ada. And I can’t call it close to pascal (the presence
begin/end doesn’t say much about anything - verilog also has them, but it’s all in one
the voice still claims that it is C).
Hello deathsoft
dea> The Verilog 2001 standard for loops and conditionals is sufficient
dea> in general I would recommend using VHDL (it is similar to Pascal and Ada
dea> I think this will be more familiar to you) and supports if/generate and
dea> for/generate since the very first version. Plus it supports types
dea> data, like a regular programming language, which allows you to
dea> when modeling an automaton, you can see the state of the automaton in a meaningful way
dea> of text (s_idle, s_rx, etc.). In addition, VHDL supports 9
dea> valued logic, except '0' states
Hello deathsoft
Yes, yes. Already announced, time of release indicated (some quarter
7 years), , approximate prices (I just don’t understand about these prices: whatever you want
consider either 2000 bucks for 1000 pieces, or for a batch of 1000 pieces 2 bucks per
piece).
When I gave a link to Alter’s FTP, I indicated this file:
61_quartus_windows.exe was downloaded to me. I decided that Web-edition
called 61_quartus_free.exe, also not small, 400 meters. What is it
61_quartus_programmer.exe (50 meters) I didn’t understand at all. The screensaver seemed to be
the same, but I did not continue the installation.
Hello deathsoft
Unfortunately, there are situations when using other people's libraries without the original one
code is impossible. For example: Jpeg, Jpeg2K, Mpeg, Tiff... What is in the open
form, it’s terribly slow, and in the case of Tiff, half of the formats are not
understands. The saddest thing is that there is no normal description of the algorithm, from
which you could make your own code, and the one that already exists in open form,
does not provide an understanding of how this can be done differently or anything
optimize. It’s easier to just spit and take it ready-made in the form of compiled
jbj files, and wait for everything to crash.
Crooked hands may be the result of a simple typo. The problem is that on x86
you will not be able to detect 10% of such typos immediately, and in the case of normal protection
- 0.1%. If you think that a programmer’s work is worthless, then you can
stay with your opinion. But the fact that it costs much more than iron
this has been known for a long time. Software is now golden compared to hardware, precisely because
that you need a lot of different software, but hardware just clones the ancients
lizards. The same arm. Forgive me, but this is a copy of our Soviet three-address
machines: Nairi, BESM4. Good progress...
Hello deathsoft
well, how incomplete. He supports everything. I just haven't received the tutorial yet
by mail, but on the Internet they only cut up bits of meat for free. I note that according to VHDL lies
much more. And there are also more implementations of soft processors on opencores in VHDL,
than in Verilog. But I still don’t like VHDL. It was enough to read
Steshenko’s comparative book (it seems), from it it is immediately clear that on verilog
the text is much shorter. I especially liked the concatenation in { }.
Well, here's the answer on electronix.ru. generate for. I immediately asked in Google verilog
"generate for" and found 2 pdfs with a description of the syntax and examples
use. And why did it stick with me exactly `for - I can’t find anything on it
succeeded...
Hello hero
her> $2000 per piece for batches of 1000 pieces
her> piece by piece maybe all 3000$
Now it’s finally clear. Golden straight. But I think these prices are not
forever. Remember how much a 1GB flash drive cost a year ago (~1000 euros), and how much
Now it costs 4GB (~100 euros). If they make more, the price will go down. I generally kiss
fit, if not into a cyclone2, then at least into a stratix. They're also a bit expensive for now.
true. But if you do nothing, then nothing will happen by the time they
will become cheaper.
So did I download the web edition (in the sense of not me, but me) or the full version? How to find out?
:v2_crazy:
Hello hero
no, send it away.
Error (10170): Verilog HDL syntax error at OperRegQueue_step1.v(25) near text
"for"; expecting an identifier ("for" is a reserved keyword ), or "endmodule",
or a parallel statement
It worked inside the always-block (I already tried it before), but there’s no
calls to modules are just a set of assignments.
Hello, Vladimir Kladov
$2000 per piece for batches of 1000 pieces
piece by piece maybe all 3000$
Hello, Vladimir Kladov
The complete Quarus in the set has
Quartus
ModeSim
IP Cores
NIOS
and like something else
And it weighs something like 1GB
WEB is about 300 meg and there is almost nothing, but the enema is suitable either to full or to
a stripped down version.
Hello hero
Well SystemVerilog is from a slightly different song
So something like that
┌─- CODE ───
integer I;
for (I:=0;I<16;I++)
OperRegQueue_mux1 ( clk, in_free_flgs[(I+1)*4-1:I*4], I ,
in_empty_triads[I],
out_write[I], out_nums[0][I], out_nums[1][I], out_nums[2][I],
out_reset_flgs[(I+1)*4-1:I*4] );
└── CODE ───
PS: I don’t understand the syntax of loops much because it usually rarely comes to this, you
Read the Verilog specification very succinctly, I’ll remember how
It's called - I'll post a link.
In IEEE 1364
Hello, Vladimir Kladov
Vla> And I also don’t understand why write the same thing 3 times. In Entity, in
Vla> Architecture, and also (I don’t remember what it’s called) in implementation.
Vla> I can read it. Well, I almost can. But writing - well, well.
Roughly speaking, this is similar to C's ifdefs. If the chip is such and such, then we determine
constants (as an example) and delays like that. If the chip is different, then all the data is too
others. Can be compared to an empty board on which sockets are soldered under
microcircuits. Plus, it is a strongly typed language compared to Verilog.
Hello, Vladimir Kladov
Vla> Architecture
Architecture - specifies the variation of architecture, for example behavioral (for
modeling) and synthesized (optimized to gate levels, for example).
And Entity defines a general abstract access interface while hiding the implementation.
Hello, Vladimir Kladov
Vla> Yes, I understand everything. It’s just, as English speakers say, too verbose, not
Vla> I like a lot of chatter. Even more so in a programming language. I'm better
Vla> I will write detailed comments in my own Russian.
Why would this be too verbose? On the contrary, "with a slight movement of the hand, the trousers
turn"... Without much effort, you can customize the project to its specific features
another stone, that's the point. Or do not update any part of the project
touching the others.
Hello icebear
ice> Why is this too verbose? On the contrary, "with a slight movement of the hand, trousers
ice> turn"... Without much effort, you can configure the project to
ice> features of another stone, that's the point. Or update any
ice> part of the project without affecting the rest.
Well, `define is also available in verilog. And `include is where you can put what
is "features". And I look at the body - the same thing has been written a bunch of times,
for what - it is unclear. 1 time is enough for me.
Hello, Vladimir Kladov
But no one knows how to tell a specific register to be exactly on
triggers, and not made on memory? The infection quartus stuck a long register (96
bit) in ram, and he himself shows in his time analyzer that in this case
brakes appear: the frequency of the clunk has decreased by 3 times. Gad. Gad. Bastard. Gad.
Hello, Vladimir Kladov
Vla> But no one knows how to tell a specific register to exist
Is Vla> made specifically on triggers, and not on memory? The infection stuck the quartus
Vla> is a long register (96 bits) in ram, and it shows itself in its own
Vla> time analyzer, that in this case there are brakes: clock frequency in
Vla> decreased 3 times. Gad. Gad. Bastard. Gad.
Do not use quartus components, but describe the register yourself using verilog,
then Quartus will not push it into memory (either through attributes/pragmas for
Verilog disable optimization).
Hello, Vladimir Kladov
Vla> My concern now is how to correctly interpret his reports
Vla> analyzer timing.
The reports show a lot of things, the best time, the worst time, etc., there are
output of the critical path (viewing it on the chip topology).
Hello, Vladimir Kladov
It is also necessary to take into account delays on external pins (5ns for each pin from
body)
Hello deathsoft
dea> Do not use quartus components, but describe the register yourself
dea> veriloge, then the quartus will not push it into memory (or through
dea> attributes/pragmas for verilog disable optimization).
Didn't use it. He stuffed it himself. As a result, I removed the directive. But what's funny
When I deleted the directive back, it no longer does this. Did I remember?
My concern now is how to correctly interpret his timing reports
analyzer. Then he says that everything is fine 420 MHz - MET. At the same time it shows 6
ns (and this is clearly not 420 MHz). Then at 5 ns he starts yelling that the frequency is needed
reduce to 200 MHz (it’s clear, it’s necessary - but why is he happy with everything about 6 ns,
on the smaller model - on a simple adder).
Hello deathsoft
dea> The reports show a lot of things, best time, worst time and
dea> etc., there is an output of the critical path (view it on the topology
dea> crystal).
Hmm. I only saw From and To there. And if I have from this From to this To
several paths, then guess for yourself on which arc it stopped. or
Do I need to do something so that he can show me the whole way?
Hello, Vladimir Kladov
It seems that the quartus had a separate Show Critical Path function (although maybe I’m confusing
with Synplify Pro, this function is definitely there, I don’t have Quartus as such
used because it gave rather mediocre results compared to
professional tools such as Synplify Pro and Leonardo Spectrum).
Hello deathsoft
Well, I simply have nowhere to get a new Synplify. What they sent me on disk - 2003
Already a piece of junk. Although it compiles very quickly. It's a pity that for old chips, but
So I wouldn’t have seen that the interface was already a little old. I don’t know where the new one is
do people take synplify?
Hello, Vladimir Kladov
Vla> Don’t know where people get the new synplify?
Through the forum of television systems "in the bins of the motherland." www.telesys.ru, there is a forum and then
ask and search. But in principle, before it was possible to download from the native site, but
then find a cure on the internet.
Hello, Vladimir Kladov
Vla> What they sent me on disk - 2003. Already junk.
Well, I think I actually had a 2001. (7.3 or 7.03)
Hello deathsoft
I want to immediately test for cyclone2 at least, and its time characteristics
take into account. And there is a cyclone even without Roman numerals, 50 MHz maximum.
Hello, Vladimir Kladov
Then you need a fresh Synplify Pro, in addition, the results that Synplify produces
Pro - inaccurate. The Synplify Pro output (.edf file) must be passed through a quartus, and
look at the time parameters already in the quartus (since only the quartus does
final placement of cells inside the FPGA). There is also such a package as Amplify,
he also does physical exercises. placement. (but I've never used it).
Here fill in your name and email and they will give you a download of Synplify Pro, then search
medicine
http://www.synplicity.com/downloads/download1.html
Hello deathsoft
This is understandable. I found where to get it, it will be available in a while. I'm just getting started
get tired of the burden of the quartus. Compile a small project in 2 minutes,
to get new timings is too much for me. That's why I'm in programming
switched to Delphi because it is not as cumbersome as any C compiler. And when
The initial adjustment is done, then you can already torture the quartus...
Hello, Vladimir Kladov
Vla> And when the initial adjustment is done, then you can already have a quartus
Vla> torment...
Well, that’s why I used Synplify, everything compiles there in 3 seconds,
Then I simulated it, checked that everything was without errors, and at the very end you can
compile with quartus.
Hello, Vladimir Kladov
Vla> it's not a problem, I'm sending it. I now have a problem with ActiveHDL 7.2. Ie
Vla> this is not so urgent, but the remedy I have does not help. B
Vla> license says something strange, like add features and salt here yourself
Vla> (why is there salt in the license?). I tried to take the content from version 6.2, but
Vla> does not work.
if you suddenly find seasonings for ActiveHDL - please share
Hello deathsoft
It's not a problem, I'm sending it. I now have a problem with ActiveHDL 7.2. Those. that's not true
It’s urgent, but the remedy I have doesn’t help. The license says something
strange, like add features and salt here yourself (why is there salt in the license?). Tried it
take content from version 6.2, but doesn't work.
Hello, Vladimir Kladov
Vla> salt
"salt" is sault vaule? In English, "salt" in encryption means noise.
(random sequence of bytes).
Hello deathsoft
Yes, it's written in Russian :)
Hello, Vladimir Kladov
Vla> yes it is written in Russian
So maybe they translated things like Promt and the like with an auto translator.
Hello, Vladimir Kladov
By the way, on a large project, Simplify is no longer lightning fast. And terribly picky
(although this is good: quartus didn’t tell me anything, but simplify gave me about fifty
warnings, of which a good third were relevant). It's even urgent for me
I had to make a utility to translate Russian comments into transliteration and
back: it turns out he really doesn’t like Russian letters. And when you try
typing a Russian letter in your editor simply falls out.
Hello, Vladimir Kladov
what, a license? There's text:
; You can add FEATURES and salt to taste :-)
That's all. I think if there were translators, the word FEATURES would definitely be translated at the same time.
Hello, Vladimir Kladov
Vla> And when you try to print a Russian letter in your editor, simply
Vla> falls out.
Write them a bug report, maybe they will fix it in the next version. I'm something like that too
I remember that there were problems with Russian letters, I was just writing comments on
English
Hello, Vladimir Kladov
Vla> quartus didn’t tell me anything, but simplified gave me about fifty
Vla> warnings
Quartus sometimes just silently synthesizes complete crap, which is then only visible
during modeling, because Previously it was not possible to watch RTL in the quarter
level, and in sinplify it was from the very beginning.