420 MHz on CycloneII?

Hello, Vladimir Kladov Here are the first results. This happens on 1 beat, on 1 small (but important) device. It seems that 420 MHz is close to the limit of what is possible on the CycloneII, but It's unclear what it would be like on a faster chip. Web Edition fails with choice chip, infection. Info; Clock; "clk" Internal fmax is restricted to 420.17 MHz between source register "OperRegQueue_mux1:mux0|out_num3[0]" and destination register "OperRegQueue_mux1:mux0|out_num3[0]" Info; fmax; restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path. Info; +; Longest register to register delay is 0.407 ns Info; 1:; + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X83_Y1_N25; Fanout = 2; REG Node = 'OperRegQueue_mux1:mux0|out_num3[0]' Info; 2:; + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X83_Y1_N24; Fanout = 1; COMB Node = 'OperRegQueue_mux1:mux0|out_num3[0]~11' Info; 3:; + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X83_Y1_N25; Fanout = 2; REG Node = 'OperRegQueue_mux1:mux0|out_num3[0]' Info; Total; cell delay = 0.407 ns (100.00%) Info; -; Smallest clock skew is 0.000 ns Info; +; Shortest clock path from clock "clk" to destination register is 2.906 ns Info; 1:; + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. =PIN_T2; Fanout = 1; CLK Node = 'clk' Info; 2:; + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 192; COMB Node = 'clk~clkctrl' Info; 3:; + IC(1.266 ns) + CELL(0.537 ns) = 2.906 ns; Loc. = LCFF_X83_Y1_N25; Fanout = 2; REG Node = 'OperRegQueue_mux1:mux0|out_num3[0]' Info; Total; cell delay = 1.526 ns ( 52.51 % ) Info; Total; interconnect delay = 1.380 ns ( 47.49 % ) Info; -; Longest clock path from clock "clk" to source register is 2.906 ns Info; 1:; + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'clk' Info; 2:; + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 192; COMB Node = 'clk~clkctrl' Info; 3:; + IC(1.266 ns) + CELL(0.537 ns) = 2.906 ns; Loc. = LCFF_X83_Y1_N25; Fanout = 2; REG Node = 'OperRegQueue_mux1:mux0|out_num3[0]' Info; Total; cell delay = 1.526 ns ( 52.51 % ) Info; Total; interconnect delay = 1.380 ns ( 47.49 % ) Info; +; Micro clock to output delay of source is 0.250 ns Info; +; Micro setup delay of destination is -0.036 ns Ладно, пойду пока 2ю ступень этого конвейера рисовать в verolg'е.