Sprinter computer architecture

Hello, All From: Ivan Mak Date; Thurs; Sep 7 2000 2:56 pm Area; fido7.zx.spectrum; ┌─- code ─── Greetings, All! === Cut === Sprinter computer architecture. Introduction. This description assumes certain knowledge of the reader, namely, knowledge of the ZX-Spectrum computer architecture and its varieties, in in particular Pentagon-128 and Scorpion-256, as well as knowledge of the BASIC language and some familiarity with Z80 assembly language. Here I will call machine configuration - a specific implementation a specific circuit in a reprogrammable logic chip (FPLM). This means that the machine has many configurations, each of which has its own scheme. I also use the concept of CACHE-RAM. This is not a cache in the formal sense sense, but fast RAM in which the processor can operate at high frequency without waiting. Cache is a RAM called only by tradition, similar to the cache on the KR537RU10 in Pentagon-128 computers. Brief information about the Sprinter computer. Processor. . . . . . . . . . . Z84C15 Clock frequency. . . . 21MHz/3.5MHz RAM. . . . . . . . . . . . . . 4096Kb RAM CACHE. . . . . . . . . . . . . 64Kb ROM. . . . . . . . . . . . . . .128Kb Video RAM. . . . . . . . . 256Kb(512) Disk controller. . . . . Kp1818VG93 Support for 1.44Mb format. . 3.5" driveHard drive controller. . . . . IDE/AT Keyboard controller. . . 101key/AT Mouse controller. . . . . . . MS-Mouse Two slots. . . . . . . ISA-8 standard Iron emulation AY-3-8910 stereo-OUT COVOX. . . . . . . . . 8bit x 4chanel Video modes: . . . Spectrum standard GRAF 320x256x256,640x256x16, TXT 80x32 Video output to TV or CGA monitor, RGB └── code ───

Hello, captain cobalt Loading configurations. At the moment the computer is turned on, as well as after pressing RESET, all information located in the PPLM responsible for a specific configuration is erased. PPLM goes into standby mode for downloading the schematic data block. At this moment, the processor is completely disconnected from any peripherals. In his the memory address space turns out to include one ROM page and one RAM Cache page. Any entry into the processor's memory address space at this moment leads to writing data to the PPLM and the program in the connected ROM page has only one single purpose - to load data into the PPLM configurations. This same ROM page contains initial configuration data. (Currently this is the Sprinter-1 configuration.) Configuration download program checks the flag in the cache memory and, if it is set, loads data from Cache, if reset, then data from ROM. Reconfiguration is based on this computer circuits. To change the scheme, you need to load a data block into the last page of the cache memory configuration from offset #100 and set the flag, which is text the string "FLEX_10K_LOADING", written at offset #80 in the same cache page. At offset #90 you need to write down the two-byte firmware identification number. After this, you need to perform a full reset, which is carried out programmaticallyby writing to a special memory page RESET_PAGE. ROM program running upon reset, finds the FLEX_10K_LOADING flag and begins loading data into the PPLM. When in this case, it simultaneously overwrites the flag, which prevents re-downloading a new one configuration when you press the RESET button and allows you to return after "manual" reset to initial configuration. Rubbing the flag also saves you from suffering in case of connecting the wrong configuration during experiments with programs. Pressing RESET will always return the circuit to its initial configuration. Note: Internal information of the PPLM data block is proprietary information of the company ALTERA. In addition to the chips themselves, PPLM ALTERA also supplies software for wiring circuits inside the PPLM. Unfortunately, this program cannot work on computer like ZX-Spectrum and it is not expected in the near foreseeable future version for Sprinter. Therefore, the development of new configurations can be done only if you have a sufficiently powerful machine (everything was done on a Pentium-166) and programs for wiring circuits in PPLM, the price of which is hundreds of US dollars. In this regard, Sprinter currently has several specific configurations, two of which are stored in ROM, and the rest can be loaded from a floppy disk or hard drive. We are constantly improving specific configurations and development of new ones.

Hello, captain cobalt Sprinter-1 configuration. Includes Spectrum-128/256 configuration, memory allocation up to 4Mb, extended screen with Spectrum, Text-80x32, Graf-320x256x256 modes, controller floppy drive, hard drive IDE controller, AT keyboard controller connected like ZX-Keyboard, 8-bit COVOX. This configuration is as close as possible to the ZX-Spectrum configuration and allows work on regular Spectrum programs and gradually change them to suit extended screen and memory modes, as well as for working with new devices. Sprinter-2 configuration. Includes Spectrum-128/256 configuration, memory allocation up to 4Mb, extended screen with Spectrum, Text-80x32, Graf-320x256x256 modes, controller floppy drive, hard drive IDE controller, AT keyboard controller (built on internal serial port of the processor), Accelerator, COVOX. The configuration, like Sprinter-1, is close to the Spectrum one, but has more strict requirements for software compatibility. Allows you to use accelerator of operations with main and video RAM. Accelerator speeds up operations transferring blocks of data and filling RAM with one byte to the physical limit speed of the main RAM. In the latest version it also allows you to speed up logical processing of data blocks using the AND, OR and XOR functions. Configuration ZX-Spectrum-256/AY.This configuration is as close as possible to the ZX-Spectrum-128/256 and includes circuit of the music coprocessor AY-3-8910. This configuration does not have advanced screen modes. The second version of the AY circuit includes three voice generators, a noise generator and amplitude regulators. There is no envelope generator. Also missing ability to read coprocessor data ports. In the third version of AY, these shortcomings are supposed to be eliminated. Game-1 configuration. Similar to Sprinter-2 configuration. The accelerator does not have logical functions, but for audio output has COVOX-Blaster - COVOX with buffer RAM allowing output sound block by block and free up CPU time for other work. The configuration is intended for use in games for Sprinter. DooM configuration. It is a further development of the Game-1 configuration. The accelerator has additional function for hardware stretching/compression of vertical and horizontal lines.

Hello, captain cobalt Organization of video memory and video modes. The Sprinter's video RAM is 256 kilobytes. In the future it is expected expansion up to 512 kilobytes for higher resolution modes. In the Spectrum screen mode, the entire organization is the same as in the standard one ZX-Spectrum. In other modes, the Sprinter screen is turned on, the structure which includes the Spectrum screen as part of the circuit. Screen device. The entire screen is divided into squares, the size of a standard Spectrum familiar place. Each square has its own output mode, as well as the address of the video RAM from where output is made to this square. Each familiarity location can have its own output mode. Currently Now you can set the following modes: ZX-40 - normal Spectrum mode with one bitplane and one attribute on familiar place. ZX-80 - A mode similar to the Spectrum one in the structure of the symbols, but in each In a familiar place there are two symbols, compressed horizontally. G256-8 - Graphics mode. A square is an 8x8 array of dots. B each point is assigned one of 256 colors, selected from a palette of 16 million flowers. Squares can have different palettes. Such palettes for the G256-8 mode - four. G16-16 - Graphics mode. A square is a 16x8 array of dots.Each dot has one of 16 colors, selectable from a palette of 16 million flowers. Just like G256-8, one of 4 can be installed in a square palette Graphics mode palettes overlap each other. Palette The 16-color mode is the first 16 colors from the 256-color palette. BORDER - The color of the border is displayed in the square. BLANK - The square is extinguished - it turns black. The square mode data size is 2 bytes, so changing the mode is only screen is reduced to rewriting 2.5 kilobytes of data in video RAM. This screen structure makes it easy to scroll both and parts of the screen according to familiarity. The screen mode is set when turned on, as well as using BIOS functions. BIOS functions allow you to open graphic and text windows on the screen in in the right places and in the right size. The BIOS has functions for opening the graphic screen to full screen 320x256 points. After opening this mode, the screen is: set of 256 lines, 320 bytes long. Adjacent points in a line are adjacent bytes. Lines are switched through PORT_Y, in which the number is set line displayed on the screen. Line numbers are counted from the top of the screen, starting from zero. To output to a graphic screen, you also need to open the corresponding main RAM page. This page will contain a copy video images.Video RAM is shadow RAM, so information residing in main RAM is under which the video RAM is located will not necessarily match the information located in this video RAM. Video data can be recorded without rewriting data in the main RAM, which is useful when working, for example, with sprites. To work with sprites, there is also a recording mode in video RAM with transparent color. In this mode, information transmitted to The video RAM is checked for the presence of the #FF byte. If this byte is detected, then the recording cycle is skipped and the data that remains on the screen in this place is were earlier. This way you can quickly draw sprites on the screen, which are rectangular pictures with “transparent” colors. An example of a program for displaying a rectangular image on the screen: ┌─- code ─── PAGE3 EQU #E2 RGADR EQU #89 LD A,#50 ; graphic video screen page OUT (PAGE3),A ; set to PAGE3 LD HL,Pucture ; image address (Direct Data) LD DE,#C040+HorPlace ; horizontal position of the picture on the screen LD A,VerPlace ; vertical position of the picture on the screen OUT(RGADR),A LD B,VerSize ; picture height LOOP; PUSH; DE ; remember the position on the line PUSH BC; remember altitude counter LD BC,HorSize ; picture lengthLDIR ; copy line POP B.C. POP DE INC A ; next Y coordinate OUT(RGADR),A DJNZ LOOP; repeat as many times as necessary └── code ─── Controlling the display mode (enable output with transparent colors, disabling copying to the main RAM) is carried out through the low-order bits of the port graphic screen pages. Accelerator of operations with RAM. RAM Operations Accelerator is designed to speed up forwarding operations data or by filling the RAM with one byte. The accelerator is present in purely Sprinter configurations and therefore does not interfere with the operation of conventional Spectrum programs. The accelerator is based on fast internal RAM in the PPLM. Operations by data transfers are carried out by writing a block of data to this internal RAM, and then copying it to the desired memory location from this RAM. After one entry copying can be done several times and in this way you can make filling the screen with textures. A different accelerator mode is used to fill the screen with one color. B instead of the copied data block, a recording is made from the internal RAM data from the processor bus, which does not change at this moment. The data block written to the accelerator RAM can have a different length from range 1..256 bytes.The accelerator is controlled directly from the program. For this processor instructions are used, which are actually operations like NOP. These are the commands LD A,A; LD B,B; LD C,C; LD D,D; LD E,E; LD H,H, LD L,L The purpose of the commands is as follows: LD B,B - turn off the accelerator. LD D,D - turn on the accelerator in the mode of receiving block size bytes, then follow command like LD A,dat, where dat will be the new block size. If block size was installed previously, you don't have to install it. LD C,C - Fill operation - filling with one byte. Subsequent LD type command (HL),A will cause the previously specified number of bytes to be filled with the value of A LD E,E - Fill operation for a graphic screen - filling vertical lines. LD H,H - reserved LD L,L - block copying. A subsequent command like LD A,(HL) will result in filling the accelerator RAM with data from the address (HL), and the command type LD (DE),A will result in data being overwritten from the accelerator RAM to the main or video RAM. LD A,A - copy block for graphic screen is similar to LD L,L command, but works with vertical screen lines. Example of using the accelerator: ┌─- code ─── ; We assume that the screen page is already open at address #C000 LD HL,#C040 ; address of the start line of the first screen LD DE,#C180 ; address of the beginning of the line of the second screen LD BC,#140 ; horizontal screen lengthDI; disable interruptions for working with the accelerator LD D,D ; turn on the accelerator to set the block size LD A,0 ; set block size - 256 bytes LD A,A ; set the accelerator to copy ; vertical lines. LDIR ; copy ! LD B,B ; turn off the accelerator EI; enable interrupts └── code ─── This section of the program will copy the entire screen from one screen to another. Its execution time is approximately 1.2 int. Additional accelerator functions (AND, OR, XOR) work in the same way way. To perform logical functions, XOR (HL) instructions are used; OR (HL); AND (HL). An example of encoding a block of 256 bytes. ┌─- code ─── LD HL,ADRES_1 LD DE,XOR_DAT D.I. LD D,D LD A,0 ; number of bytes to encode LD L,L LD A,(DE) ; take the data block into the accelerator RAM XOR(HL); perform an XOR operation with accelerator data LD(HL),A ; store the result of the operation in RAM LD B,B EI └── code ─── The speed of the accelerator is limited only by physical speed operation of the main RAM. You can determine the time a team works with the accelerator by with this approximate formula:Working time = team working time without accelerator + working time accelerator Accelerator operating time = number of bytes sent / 7000000 (seconds) Disabling interrupts while the accelerator is running is necessary because at this moment the processor command system and the program on interrupt will not be able to work normally. === Cut === The Protoss have fled. The Zerlings took off. It's time for me to call it a day. Ivan. - Divorce the circuit, big and small... [ Sprinter-II ] [Forth-CPU] [ZX]

Hello, captain cobalt Memory allocation scheme. The memory allocation schemes in the Sprinter-1 and Sprinter-2 configurations are the same and quite transparent. In fact, it represents a distribution scheme memory of the Scorpion computer, with an additional circuit superimposed on it, which allows you to randomly set all memory pages, both ROM and RAM. Each page of ROM or RAM has its own port, which indicates actual page number out of 256 pages of all 4Mb. Pages, projected into various windows of the processor address space have their own own ports. Those. The page included in addresses #4000..#7FFF, and the page number 5 of the usual Spectrum memory allocation, included in the addresses #C000..#FFFF have separate ports. There are 32 such memory page ports in total. 16 ports are responsible for RAM page numbers connected to addresses #C000..#FFFF. Three more ports are responsible for connecting RAM pages to addresses #0000..#3FFF, #4000..#7FFF and #8000..#BFFF. Eight ports are used for connection various ROM pages. One port is for connecting a cache page instead of a ROM. And one port is the port of the system ROM, which is connected in place of the ROM immediately after Resetting the machine using the Ctrl+Alt+Del keys. The remaining 3 memory page ports remain in reserve for now. Schemememory allocation allows you to connect to the processor address space not only RAM or ROM, but also ports and memory of ISA cards inserted into the slot. When connecting Scorpio extended RAM pages to addresses #C000..#FFFF, slots can be redirected in their place. To do this, you just need to write to the port one of these pages is the value corresponding to the ISA slot to which an appeal needs to be made. This value also indicates what is being done access to ports or memory. ┌─- code ─── Sprinter memory distribution scheme. Address space Computer ROM page ports processor connected pages 16k pages --------------- -------- --------------- --------------- | #0000..#3FFF +->+ ports +-->+ ROM_BASIC +-->T--T--T->+ EXPANSION | | | | #7FFD,| +--------------+ | | | +--------------+ | | | #1FFD +- | ROM_TR-DOS +-->+ | +->+ TR-DOS | +--------------+ L-------- | +--------------+ | | | +--------------+ | #4000..#7FFF +--------- | | | | | +->+ BASIC128 | | | | | +- - - - - - - + | | | +--------------+ | | | | | ROM_SYSTEM +-->- | +->+ BASIC48 | +--------------+ | | +--------------+ | | +--------------+| #8000..#BFFF +---- | L>+ RAM_0000 +---> | +->+ SYSTEM ROM | | | | | L-------------- | | | +--------------+ | | | | --------------- | | +->+ SYSTEM ROM2 | +--------------+ | L-->+ RAM_4000 +--->+ | | +--------------+ | #C000..#FFFF + | L-------------- | | +->+ CONFIG 2 | | || | | | | +--------------+ | || | --------------- | | L->+ CONFIG 1 | L---------------| L-------->+ RAM_8000 +--->+ | L-------------- | L-------------- | | | | | Computer RAM | -------- --------------- | | 16k pages | | Ports +-->+ RAM_0 +--->+ | --------------- | | #7FFD,| +--------------+ +--->T->+ RAM_00 | L>+ #1FFD +-->+ +--->+ | | +--------------+ | | +- - - - - - - | | | +->+ RAM_01 | | +-->+ RAM_7 +--->+ L->+ +--------------+ | | +--------------+ | | | | | +-->+ RAM_8 +->T-|--->+ +- - - - - - - +| | +- - - - - - - + | | L--+ RAM_7F | | +-->+ +->+ | +--------------+ | | +--------------+ | L--->T->+ RAM_80 | | +-->+ RAM_F +->+-> | +- - - - - - - + L--------L-------------- | | | | External Devices | | +--------------+ ------------------- --------------- | +->+ RAM_FE | Ports +---->+ ISA_1 +<----+ | +--------------+ computer | +--------------+ | L->+ RAM_FF | +---->+ ISA_2 +<----+ L--------------- | +--------------+ | +---->+ HDD +<----+ | +--------------+ | +---->+ OVER DEVICES +<----- -------------------- L-------------- Figure 2. └── code ─── In other configurations, the memory allocation scheme is simplified to free up PPLM resources. Ports #1FFD and #7FFD may be missing, and it is also simplified scheme for working with memory-mapped devices.

Hello, captain cobalt Port distribution diagram. Sprinter has two separate groups of ports. The first group is internal ports of the Z84C15 processor, the second - external ports. Addressing ports of the first group cannot be changed since these ports are on the same chip as the processor. The second group is connected via PPLM and their addresses can be changed as desired, with the only condition that it does not intersect with the addresses of the first group. You can read about what ports are available on the Z84C15 chip in the documentation for this processor and here I will mention some of them. One of the consecutive ports are used for input from the active mouse. One of the parallel used for data output, signals are connected to the second parallel port interrupts and direct access requests from ISA slots. Parallel port The Z84C15 processor is designed in such a way that it is possible to organize interrupts for signals coming through the parallel port. Actually the second The parallel port is used as an interrupt controller. The port distribution scheme of the second group has its own peculiarity. The main idea it was possible to quickly change the configuration of ports without overloading PPLM. This is achieved by using a port allocation map, located on a special page of RAM. When a port access cycle appears, the card's RAM is first accessedports. The port map records which port is connected to a given address. Next, internal decryption occurs, byte by byte, from the port map and access to selected port. In non-turbo mode this happens without any delays, and in In turbo mode, the WAIT signal is set to the processor depending on the required port access cycle length. To connect to or disconnect any port from any address Just open the port map and enter one byte in the right place. The port map page contains four maps that can be switched via the system port. This way you can quickly switch port configurations, which can be useful when running Spectrum programs together with Sprinter's BIOS. Specific port addresses used in Sprinter. Here I will provide port addressing for Sprinter-1 and Sprinter-2 configurations. I would like to note right away that these addresses can easily be changed by a simple program, in if such a need arises. Standard ports. #FE - RD_KBD - keyboard port #FE - WR_BRD - curb port #7FFD - ZX-Spectrum 128k expansion port #1FFD - Scorpion ZS-256 expansion port #1F,#0F - RD_KEMPS - joystick port. In the Sprinter-1 configuration, port #1F hardware forwarded to port #0F #BFFD,#FFFD - AY-PORTS - AY coprocessor ports (ZX-Spectrum-256/AY) Not exactly standard ports.#FB,#4F - COVOX port. Additional 8-bit Sprinter ports. #82 - PAGE0 - RAM page, connected instead of ROM via port #1FFD #A2 - PAGE1 - RAM page connected to address #4000 #C2 - PAGE2 - RAM page connected to address #8000 #E2 - PAGE2 - RAM page connected to address #C000 It should be especially noted here that through port #E2 you can change any of the 16 pages Scorpio memory allocation. #89 - PORT_Y - vertical coordinate of a point on the graphic screen or page VIDEO-RAM for Spectrum mode #C9 - RGMOD - screen mode port. Switches screen mode pages. #3C,#7C - SYS_PORT - it is not recommended to touch the system port #10..#1F,#EE,#EF,#F0,#F1,#F4 - internal ports of Z84C15 RAM page ports are open for both writing and reading. This makes it easy execute programs that use page switching and then return those pages back. When the BIOS is running, all pages are saved. Additional 16-bit Sprinter ports. #xx50..#xx55 - HDD ports - not recommended for use by external programs. Functions for working with HDD are recorded in ROM. Hidden Sprinter ports. Hidden ports are ports that are not available at a particular time, but may become available after changes are made to the port map. Their addresses are not are indicated because they can be placed anywhere. BASIC48 ROM port BASIC128 ROM portTR-DOS ROM port EXPANSION ROM Port ROM SYSTEM port New ROM firmware can be installed through these ports. There are enough of them for this write to RAM with page numbers less than #80 and write to the corresponding port this page number. With this connection, the pages These pages will be protected from recording. Partially hidden, ports #7FFD, #1FFD are also in their normal state are write-only, but values written to these ports can be read by opening the appropriate ports for reading. In other configurations, some ports may be missing or present new ports.

Hello, captain cobalt Technical implementation. The core of the machine is the Z84C15 processor and EPF10K10QC208 PPLM. Besides them on the board there is a ROM chip, 72-pin SIMM for 4Mb, 256Kb video RAM, 64Kb Cache-RAM, disk drive controller circuit based on LSI KR1818VG93, buffers for connection joystick, tape recorder, printer, keyboard, disk drives, hard drive, mouse, ISA-8 bus buffer chips and another PPLM from ALTERA - EPM7032LC44. This PPLM does not change its configuration and is designed to ensure synchronization and initial startup of the computer. The board also provides the ability connecting CMOS clocks based on the DALLAS chip. In addition to peripherals and buffers there are decoding chips, the inputs of which are connected to the processor via PPLM. This allows you to easily change device addressing without any modification PCB layout. Machine architecture capabilities. The computer circuit is based on a large reprogrammable logic chip. Connecting peripheral devices via PPLM allows you to get high machine flexibility in configurations. Programming of the PPLM is carried out immediately at the moment of switching on, and so the same during a reboot, which allows you to radically change the scheme in the PPLM directly during work. This makes the computer architecture stand out from number of existing computers and therefore many concepts inherent in conventionalmachines change their meaning. In fact, the computer has a changeable architecture, in which changes are possible in many parts of the circuit. So, for example, it is impossible talk about specific addresses of peripheral connection ports, since they can be changed in one second by reprogramming the PPLM and data in RAM, responsible for port configuration. Specific addresses appear only in specific configurations, for example, such as the ZX-Spectrum configuration. The reprogrammability of the circuit gives quite a lot of freedom to the programmer's imagination according to machine configuration. When conceiving a specific job, a programmer can determine in what configuration it can be made better, and perhaps come up with your own configuration, which can then be implemented in PPLM and enabled before running this program.

Hello, captain cobalt ┌─- code ─── Block diagram of the Sprinter computer. -------- ---------------------- ------------->Sinc |Printer| | 2 ISA SLOTS | | --------->R +-------+ L---T-T-T-T-T-------T-T-T-T-T--- | | ------>G | Mouse | ----+-+-+-+-+-------+-+-+-+-+-- | | | ---->B L-T-T-T-- | Buffers and decryptors | | --+-+-+- | | | L---T----T-T--T-T----T-T-- | | DAC | | | | |INT | | | | | | | | buffer | ---+-+-+T- | | | | | -+-+------+- L--T-T--- --------- | Int | +----------|---------- L--| |---+ EPF10K10 +---- L------+ video | | ports | +---------|----------DATA-| |---+ +--V_DATA----+ | +-------- +----|--- ----------| |---+ +-----------+ RAM | | +<---- | | | | | | | | | +--------------------- L---+ +-----------+ | | Z84C15 +---------------ADRESS-----+ +-V_ADRESS---+ | | +---- --------------------+ +------------+ | | | | | | | | | | | | +<---| |-| |-------------->+ +--WE,CSi--->+ | | +<---| |-| |----DIR------->+ | L---------| +<---| |-| |-------------->+ +-------> Audio OUTs | | | | | | | | --------- | | --+-+-+-+------- | +------------+ MAIN | | | | ПЗУ и КЭШ-ОЗУ +<-ADR'-+ +--DATA------+ RAM | L-T-T-T--T- | CS +<-CS---+ +------------+ | | | | | L---------------- | | | SIMM | | D | | --------------- | +------------+ | | A | | | EPM7032 +------->+ +--ADRESS----+ | | T | L-->+ Sinchro | | +------------+ | | A | | HDD_DIR +<-------+ | | | | | | | ФАПЧ +<-------+ +-RAS,CAS,WE-+ | | | | L-T-T-T-T-T----- | | L--------- | | | | | | | | | | --+-+-+--------+-+-+-+-+------- | | | Периферийные устройства +<----+ | | FDD,HDD,KEMPSTON ++ | --------- | --------- | | | TAPE +<--- |Keyboard+--------->+ || in/out | +TTTTTTTT+ | | L--------- L++++++++- L----------- Figure 1. └── code ─── For simplicity, some buffers and decoders are not shown in the diagram. Quantity The wires in the tires are also conventional. Part of the control signals of devices with PPLM multiplied with SIMM addresses. The following description of the architecture is a description of specific configurations and parts of configurations. But before that, a few words should be said about switching the configurations themselves.

Hello, captain cobalt The source "from" is lost File: sp2k_sch.rar http://zx.pk.ru/attachment.php?attachmentid=3549

Hello, CHRV CHR> I have a bunch of documents on Spriter. I'm ready to give them to anyone. CHR> Including all of Imak's answers to FIDO, and clippings from the forum on CHR>Petersplus. And all this with a parent present ;)

Hello, CHRV Do you have ROM and Alter firmware?

Hello, ilyaspb ily> The source “from” is lost I have a bunch of documents on Spriter. I'm ready to give them to anyone. Including all of Imak’s answers to FIDO, and clippings from the forum on Peterrsplus.