Interrupt system - have questions.

Hello TomCaT Tom> LD A, R Tom> LD I, R flags 3,5,7 are copied from A. CF does not change, ZF=1 if A=0. PV is placed in depending on whether interrupt is enabled Tom> But, I suddenly discovered that I don’t understand at all how IM 0 differs from Tom> IM 1 (for Speccy, not for Z80)? To do this, you need to understand how it differs specifically for the Z80 ;) if the tire is stable, then no different for spec

Hello, All Kir> DI Kir> LD A,63 Kir> LD I,A Kir> XOR A Kir> LD (23613),A Kir> LD HL,51697 Kir> LD (23746),HL Kir> IM 1 Kir> EI Kir> Kir> Of course, VASIKA variables must be set... =) After Kir> of the above-specified ACM lines, neither break nor ignore will work, Kir> the only thing is that if there is a reading error, it will try to read forever =) I read the code. The general principle is clear - as a result of a reading error, interruption, and what happens next - that’s on the conscience of TR-DOS and/or programmer... But, I suddenly discovered that I don’t understand at all what Is IM 0 different from IM 1 (for Specky, not for Z80)? IM 2 - I know about him no need to explain... I have also long been interested in the question of how teams such as LD A, R LD I, R Maybe someone will just post a link to a book where this is explained well? -- Can you help Robin in his quest for the Silver Arrow?

Hello TomCaT Tom> But, I suddenly discovered that I don’t understand at all how IM 0 differs from Tom> IM 1 (for Speccy, not for Z80)? Open the document “User Manual Z80 Family CPU User Manual”. Page 44. Free translation. 1.IM0. This mode is the same as the interrupt mode of the 8080 (KP580). In this mode, the interrupting device can place ANY instruction on the bus that will executed by the processor. Typically these are RST nn or CALL nnnn instructions. After restart the processor, IM0 mode is enabled. Note 1 (mine, SfS): When the Spectrum bus is EMPTY, pulled up to +5V, there will be read instruction code #FF. This is instruction RST #38. Note 2 (mine, SfS): If you develop your own periphery, then it’s not a sin use IM0 mode to switch to interrupt processing from it. Especially It’s convenient that you can issue the command CALL #nnnn. Let's say, during initialization peripherals, the address of the interrupt handler is written into some of its registers, (and arbitrary, and not as in IM2), which is then substituted onto the bus in team CALL #nnnn. Page 45. Free translation. 2.IM1. When this mode is set by the programmer, then when an interrupt occurs, An unconditional transition occurs to address #38. Note 1 (mine, SfS): Since this address is the same as the jump address in IM0 mode with an EMPTY Spectrum bus pulled up to +5V, then in standardSpectrum configurations (without additional peripherals) modes IM0 and IM1 - NOT THEY HAVE DIFFERENCES! I won’t write about IM2 - you know everything yourself :) Documentation is a very useful thing :)

Hello SMT! 11 Oct 2005 you wrote: Tom>> LD A, R Tom>> LD I, R There is no command LD I,R - obviously, LD A,I was meant. S> flags 3,5,7 are copied from A. CF does not change, ZF=1 if A=0. S> PV is set depending on whether interruption is enabled But if interrupts are enabled and the interrupt pulse has arrived during the execution of the LD A,R (LD A,I) command, the P/V flag will be cleared as if interrupts were disabled. More about this here: http://ivr.webzone.ru/articles/ldar_new/ Best regards, Ivan Roshchin.

Hello, SfS Yes, I knew about the documentation, alas :( , but for everything else (and for communication) - thank you. Now I figured it out :)