IM2, interrupt vector
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Hello Robus
Rob> I saw 3+5=7 branded models
5! yes, that's 5! %))))
PS. Use the same 257 bytes and forget about the unstable bus.
Hello, All
Here's the problem I ran into. The literature says that
proprietary Spectrum48 interrupt vector I must be located in the address area
ROM, otherwise a hardware failure will occur. But some domestic Spectrums
unstable data bus, so a table 257 bytes long is created in RAM.
Of course, it would be possible to use a table in a free ROM space (where #FF), but
on many computers it is occupied by all sorts of garbage. How to ensure normal operation
IM2 on any computer?
Hello, Jukov
generate a table of 257 identical bytes in the address area #8000-#BFFF (up to
#FFFF if 48k and page 0 are used). and the table values are vectors
can be located anywhere.
Hello, Jukov
Juk> Here's the problem I encountered. The literature says that
Juk> on the proprietary Spectrum48, the interrupt vector I must be in
Juk> area of ROM addresses, otherwise a hardware failure will occur. But for some
Juk> domestic Spectrums have an unstable data bus, so in RAM
Juk> creates a table 257 bytes long. Of course it would be possible
Juk> use a table in free ROM space (where #FF), but on many
Juk> the computer is busy with all sorts of bullshit. How to ensure normal operation
Juk> IM2 on any computer?
I have a branded Speccy 128+Beta, which has no problems with vector I floating.
Actually, in my entire life I have seen 3+5=7 branded models. The first three, one of them
mine were made in Poland, the other five were in a computer club and where
I don't know if they were collected. I tested all models for this glitch and it was not there.
However, we were talking about finding register I in the range from 0 to 63, but IM at the same time
not 2 but 1! No matter how much I delved into bourgeois works, I did not see that
vector I with IM2 they used a ROM, with the exception of the Polish demo "Song In"
Lines". It is recommended in the 48k model to keep the vector in any range except from64 to 127. Otherwise, at the time of sampling bytes to generate video, any command will
performed with inhibition, and it is noticeable. And if, at the same time, you do everything
program in the range from 16384 to 32767, then the braking can be 5-6 times. A
this is a strict rule to overwrite 257 bytes with one number, I have only seen it in Durrel
Software, but they also loved them when reading the keyboard port register
invert, is this the same as considered standard? It seems to me that these shortcomings
with a glitch, the vectors came from Speccy clones!
Hello Vitamin
Vit> 5! yes, that's 5! %))))
Quarrel... Miscalculated...
Vit> PS. Use the same 257 bytes and forget about the unstable bus.
Lose 254 bytes? I won't give it away!!! I'd better put a depacker there!
Hello Robus
I've developed a new way to read DOS port #1F via interrupts. If not
our clones with an unstable data bus, then this would be the shortest procedure
read port #1F;
IN1F; LD BC,(#5BFF)
LD HL,INT
LD (#5BFF),HL
LD A,#5B
LD I,A
IM 2
LD (COPYSP+1),SP
LD A,#FF
AGAIN LD D,1
LD IY,#2D87
EI
CALL DOS
INT DI
COPYSP LD SP,0
BIT 7.A
JR NZ,AGAIN
LD (#5BFF),BC
***
DOS PUSH IY
JP #3D2F
***
#2d87 IN A,(#1F)
AND #7F
RET Z
DEC D
PUSH HL
PUSH DE
JR NZ,#2D7B
HALT
Hello, Jukov
Clever was the Pentagon, which worked as follows:
If 257 bytes are full, then everything is ok
If they have 2, but the table is some other one, the program usually worked,
but at any moment she could reset herself - actually several years before
I couldn’t understand why some programs crashed stably, and some
dumped early or late! =)
Thus, after that I always filled 257 bytes myself!
Moreover, I can note that in many branded games I saw 257 bytes filled up!
(and not just one, as someone said!!!)
Hello Robus
Rob> Lose 254 bytes? I won't give it away!!! I'd better put a depacker there!
If the bus is stable, then you can catch the value of the interrupt vector and do
interceptor at a very specific address. But if its value jumps like
saiga in the steppe, then there’s no way without a sign... unless you use pzu128 and
replace your im1 handler...
Hello, Jukov
Juk> I have developed a new way to read DOS port #1F through interrupts. If
Juk> if it weren’t for our clones with an unstable data bus, then this would be the best
Juk> short procedure for reading port #1F;
U; our “clowns” tighten the tire through the register assembly - fixes the problem.
But it’s better not to give up and make a table.
Hello fyrex
The bus is unstable on the native branded Spectrum. I don’t know exactly which ones
specifically models (easy to install using schematics, most likely Sinclair ZX
Spectrum 16, 48, 128 and +) - but all (99%) of the toys know about it. Throughout
probability, on the proprietary spec, non-use of a 257-byte table immediately
leads to a very definitely clear failure. Therefore, skip this feature
it was impossible when writing the game.
If anyone is interested, a byte of attributes is issued to the bus. This happens
because the ULA and the processor are decoupled in the proprietary circuitry simply by resistors,
and the processor “picks up” the attribute byte issued by the ULA.
Sovdepov's computers were completely free from this drawback (for
"Moscow" may be an exception). And this happened on very rare occasions
cause of incompatibility.
This can be treated on a Soviet computer by tightening up the data bus using resistors
to +5V. Resistors are needed in the range of 10...15 kiloohms.
If you have doubts about the TRDOS + 2-byte interrupt vector combination, then
I advise you not to doubt and do it. Only read TRDOS registers via
IM2 interrupts are not an "invention". This has already been used. And just like that
method, if I'm not confusing anything. As far as I remember, the point was to
enable IM2 and provide interruption for “flight” from the procedure in which
The processor would go into loop in normal cases.There is no need to count on non-Soviet computers. TRDOS is extremely unpopular among the bourgeoisie.
But Soviet computers have a stable bus. If anyone is unstable, it is very
a rare exception (Soviet spec + TRDOS + unstable tire). Such people
are very rare and can be neglected.
Hello, The Exploited
The> yeah, it was described in the ancient zx review ;)
The>
There is a big difference between the way I wrote and the review way (take a look
at least for the length of the procedure). In Revue it was necessary to select the delay between
interrupts so that when TRDOS is called, immediately after reading 1F,
interruption This is a loss of disk revolution. But what if the time is different?
different computers between interrupts? My method does not have these disadvantages. Secondly,
if register 1F is zero, the register is read instantly.
Hello Raider
Rai> If anyone is interested, a byte of attributes is issued to the bus. Happening
Rai> this is because the ULA and the processor are simply decoupled in the proprietary circuit
Rai> resistors, and the processor “picks up” the attribute byte issued
Rai> ULA.
this is true, only these attributes hang there exclusively when the beam goes along
screen, and accordingly during IHT there #FF
Rai> And this is exactly the method, if I’m not confusing anything. As far as I remember
Rai> the point was to enable IM2 and provide interruption
Rai> "crash" from a procedure in which the processor in normal cases
Rai> was looping.
yeah, it was described in the ancient zx review ;)
Rai> There is no need to count on non-Soviet computers. TRDOS among the bourgeoisie is extremely
Rai> is unpopular. But Soviet computers have a stable bus. If anyone has
Rai> is unstable, then this is a very rare exception
but this is a misconception, in the original Pentagon128 the data bus is unstable,
when the trdos ROM is connected. during int the vector is taken from the trdos port #FF
Rai> Such people are very rare and can be neglected.
impossible =(there were precedents that were quite cruel
Hello, Jukov
so I’m not talking about your method, but the one that Raider wrote - a quote for something
indicated...
Hello, The Exploited
As for why branded toys use a 257 byte table - I somehow
I read the bourgeois documentation on programming (alas, I couldn’t find it now), and there it was
it says something like “during the int, in theory there should still be FF, but all sorts of
External devices for a particular user can crap on the bus, so it’s better
play it safe." An example of such “devices” (it seems) was called
interface-1, and "in some cases" even AY!
Hello Lethargeek
Let> "during int, in theory, there should be FF, but all sorts of external ones
Let> devices of a particular user can crap on the bus, so it’s better
Let> play it safe"
The book “How to Write a Game...” also directly states this. They really forgot there
about fast memory and fussing about the latest addresses - obviously everything is under 48k.
Hello TomCaT
Can anyone explain in more or less accessible language the terms “masked”
and "non-maskable" interrupts? And almost all articles are silent about im0 and
im1. where are they used and how do they work?
Hello, Jukov
“Maskable” are those whose processing can be prohibited or allowed
programmatically (di, ei). These are all INT (im0, im1, im2). With unmasked ones like this
can't be done. Example - NMI, a program is forcibly called by a hardware signal
at address 102 in DOS
an INT signal with a frequency of 50 Hz is supplied to the processor and it decides what
case do
processing prohibited - nothing
allowed - according to the current mode (im0, im1, im2):
im0 - a command is removed from the data bus and executed. It just always works out
so that it is #FF (rst 56), so it works the same as im1 (if there is no
the piece of iron on the tire does not litter at this time)
im1 - this is where I definitely have a memory loss (it seems like I’m just doing call 56)
im2 - 2 bytes are removed from address , this is the address
interrupt handling procedures. This is where the transition is made.
Hello, SAM style
thank you! but about im1 it’s still interesting.
Hello, moroz1999
mor> thank you! but about im1 it’s still interesting.
IM 1 mode is used in small computing systems where there is sufficient
one single maskable interrupt vector. When a request is received
interrupt, the microprocessor stores the return address of the interrupted program in
stack and jumps to address 0038h. So in this mode
maskable interrupts are handled in exactly the same way as
unmasked. The difference lies in the ability to mask them and in the address
interrupt handler.