Explain about the AF register and flags

Hello Sinus memory refresh breaks described in ZX review

Hello,GriV What are you raving about, what register is F, what refresh... In proprietary specs and some clones (with two memory fields) indeed the memory was regenerated by the processor, this is done by the IR register pair (do you think why does it “snow” if I is placed in #40..#7F?), but not AF.

Hello jtn it's driving :) well, I drove it away, but how was it all done? I'm talking about the suffocation of memory via R register?

Hello Jerry 32k of memory consists of 64 rows and 512 columns. for it to retain information it is necessary select each column for reading after a period of time not exceeding passport (2ms or something for ru5). so here it is. if we don’t give for example register R goes beyond the limit of 31, i.e. it will dangle in the interval 0..31, then with at addresses #8020..#803f,#8060..#807F and then with step #20, the bits will begin to float. a on branded computers, in addition, in the regeneration cycle it is read from memory to the bus number from IR, and since the bus is common with VC and if I is in the range #40-#7f, then the data seems to be mixed and it turns out to be snow

Hello jtn yes, jtn is right. no register F is the topic here. you just need ┌─- code ─── XOR A GG LD R,A JP GG └── code ─── In Grodno, we once wrote a defense based on this. only worked on machines with two memory fields (mostly bytes).