Branded spec - good or bad?

Hello and prosperity to you, All! I was prompted to write this manuscript by the desire to clarify this the question is still not entirely clear to many, although in principle, I still don't understand some things... In the process of writing, I found both evidence of power dealers of a branded car, and the dock to Lunterovsky was investigated spec emulator (Z80). Okay, that's enough entry per capita for us! The makeshift is different for 48k and 128k cars. For 48 car: int │ (*) │ │16│ ╔═════════════════╗──│─── │ 64 ║ ║ │ │48│ ║ ███▓▓▓▒▒▒░░░──║──│──────── ║ ███▓▓▓▒▒▒░░░ ║ │ │ ║24 ███<128>▒░░░24║48│ │ 192 ║<> ███▓▓▓▒▒▒░░░<>║<>│ │ ║ ███▓▓▓▒▒▒░░░ ║ │ │ ║ ███▓▓▓▒▒▒░░░──║──│─── ║ ║ │ │ ╚═════════════════╝ │ │ 56 │ │ │ └────────────────────┘─── 312 lines x 224 bars = 69888 For 128 car: int │ (*) │ │ ╔═════════════════╗ │ │ 63 ║ ║ │ │ ║ ███▓▓▓▒▒▒░░░──║──│────── ║ ███▓▓▓▒▒▒░░░ ║ │ │ ║LB ███<128>▒░░░RB║HR│ │ 192 ║<> ███▓▓▓▒▒▒░░░<>║<>│ │ ║ ███▓▓▓▒▒▒░░░ ║ │ │ ║ ███▓▓▓▒▒▒░░░──║──│─── ║ ║ │ │ ╚═════════════════╝ │ │ 56 │ │ │ └────────────────────┘─── 311 lines x 228 bars = 70908LB+RB+HR=100 I don't know more exact values. In the dock for the Lunter emulator it was written that the first byte the screen will be displayed 14364 clock cycles (in 128k) after the appearance int. That. The ULA begins forming the screen at point (*). First it displays the middle part of the screen (or border), then the border, then the beam returns, then the border returns. Screen data sampling is performed every 4 clock cycles (the screen byte and attribute are read). The border color also changes every 4 beats. ULA with 16k of lower memory and 32k of upper memory do not work depending. If the processor wants to read or write to the lower memory, it slows down if the ULA is also reading. As far as I understand, this is achieved by using 2 address buses ca and data, which are nevertheless connected to each other through resistors. Lower memory works 15-30% slower, especially if the size Post a program there, and ULA in the 128th machine gives the processor more freedom in access to these 16k than 48th. fast memory: 70908 -> 128/+2/+2a/+3 slow memory: ~58640 -> 128/+2 ~65135 -> +2a/+3 Oddly enough, IN (#FE) slows down the processor until ULA will give the result. On average, the command "IN A,(#FE)" takes 12.15 bars, instead of the required 11. If the Z80 reads from a non-existent port, then the contents are read data buses. And because ULA does not stop, and ~62% of the time is under-When constructing a screen, bytes appear on the data bus with screen and attributes. The processor reads on its data bus what appears on the ULA data bus. ULA does not digest the interrupt vector below #8000 one by one Reason: During cycle M1 (opcode extraction), the processor outputs address bus to the low part the contents of the register R, and to the high part - contents I (for memory regeneration). At I=#40-7F, ULA is buggy, and thinks that the processor wants to read a byte from the lower 16k. ULA cannot cope with such a reading frequency and misses a byte which is intended for constructing a screen. And instead of this byte the previous one is used, which leads to the appearance of “snow” on screen. 48k/128/+2 spectra still work, and +2a/+3 are doomed to collapse. Hmm... It seems like I didn't mess anything up, but who knows? There is a certain Vectron toy that I certainly haven't seen, but it uses the hardware feature described above... And the last question is the page port. At 128/+2 out (#FD),#10/#50 works exactly like out (#0D),#10/#50 Out works on +2a/+3 (#FD),#50 That's it. If I flashed lameness somewhere, excuse me... kind of like evil Vitalik AKA Dark / X-Trade