Methods of debugging
DMA Ultra Sound Card
INTRODUCTION
So, to build a sound card, you must: landfill somewhere
melkoshem at 50, there will be more - take it, do not
press-freedom place more useful, avometr, a simple
logic probe if there is - ostsilograf
type of AML-2, N3015 (personally I do not need it), Yefim
logic, a couple of timers, a couple resistors, 8 kondesatorov
stuff, equipment wire, BIS 1810VT37, standard connector SNP64
(as the controller TR-DOS) with mating connector to the card
komputeru and most importantly - the soldering iron. Full list
of details see below.
Setup and installation is divided into several stages. If
you card is fully collected, there is no need to disassemble
it, only enough to restore the changes on the board
computer.
After desoldering the elements necessary
CAREFULLY rang all the connections on
correctness and all the neighboring chips on legs no short
circuits between them.
Particular attention should be paid to the chains
power, since errors can be derived from
down half a chip or power supply.
Well there you go ...
1. Setting up the unit DAC
01.01 soldered chip: DD21-DD28,
DA1-DA12 and related discrete
elements.
1.2 audio output is input to audio amplifier. ____ ____ ____
____
1.3 Signals CSC1 - CSC4, CSV1 - CSV4
served with more chips
555ID7, which included the following:
1.3.1 To the Pentagon:
1 __ 15 ____
A4 A0 Q0 CSC1
2 __ 14 ____
A5 A1 Q1 CSC2
3 __ 13 ____
A6 A2 Q2 CSV1
__ 12 ____
4 __ Q3 CSV2
A7 V1 __ 11 ____
___ 5 __ Q4 CSC3
DOS V2 __ 10 ____
6 Q5 CSC4
IOWR V3 __ ____ 9
Q6 CSV3
__ 7 ____
Q7 CSV4
Signals A4 - A7 are taken from the processor,
DOS with 8D76, IOWR with 10D64 Pentagon.
1.3.2 For other users:
1 __ 15 ____
A4 A0 Q0 CSC1
2 __ 14 ____
A5 A1 Q1 CSC2
3 __ 13 ____
A6 A2 Q2 CSV1
__ 12 ____
4 __ Q3 CSV2
A7 V1 __ 11 ____
____ 5 __ Q4 CSC3
IORQ -> V2 __ 10 ____
__ 6 Q5 CSC4
WR> V3 __ ____ 9
Q6 CSV3
__
___ 1k Q7 CSV4
DOS
Type diodes KD521. All signals are taken from
processor, DOS is taken from the floppy drive controller so
that when the active ROM TRDOS it was a log. 0. If you do not
know where get it, then just feed it +5
(This will not affect performance,
just work the drive will be accompanied by "sound effects").
Immediately after power supply, check how much the warmed m / s
K572PA1 if they are not heated - all normally, if they
immediately became hot - immediately turn off the power, lest
their could not sleep, and instead of 12 volts at the add m / s
received 5, on the sound is almost not affected. It is best to
use km572pa1 (Verified through personal experience) - they work
stable under all conditions.
1.4 Type test program to
the resulting "Super sound drive".
10 LET PC = 15, 31, 79, 95
20 LET PV = 47, 63, 111, 127
30 FOR I = 0 TO 63: OUT PV, I
40 OUT PC, 0: OUT PC, 255
50 NEXT I
60 GOTO 30
Once launched, you should see the sound
gradually changing the volume.
1.4.1 NOTE. Sound card has 4 channels and all they need to
be tested separately. Not to write separate programs for each
channel, for some variables will be given 4 (6, 8 or more
required amount) of option values separated by a semicolon.
Necessary to substitute the first the first values, then
second, etc. In the above example, you first need to be
replaced PC = 15: PV = 47, then PC = 1931: PV = 47, and run the
program again, etc. This record will be found in almost all
programs.
1.5 is checking that all the channels.
All channels should be clear to play
sound volume must be regulated
smoothly.
1.6 If at one or all channels
no sound, need more testing. The verification required
Special measuring instruments: an oscilloscope or logic probes,
which described in the appendix.
1.6.1 First, ensure proper
work on additional decoder. chip ID7.
1.6.1 (a) .1 We collect program:
PORT EQU # 0F; # 1F; # 2F; # 3F; # 4F; # 5F; # 6F; # 7F
DI
M1 OUT (PORT), A
LD A, # 7F
IN A, (# FE)
RRCA
JR C, M1
EI
RET
then checked the pulse of this form here: the often
that about 77 kHz at 15, 14, 13, 12, 11.10,
9 and 7 feet extra. ID7 (15 foot meets the port # 0F, 14 - #
1F, etc).
1.6.1 (a) .2 In the absence of such pulses should once again
check carefully raspayku ext. ID7 and if no errors found that
ID7 should be replaced.
1.6.1 (n) .1 We collect program:
PORT EQU # 0F; # 1F; # 2F; # 3F; # 4F; # 5F; # 6F; # 7F
DI
M1 OUT (PORT), A
LD BC, 0
M2 DEC BC
LD A, B
OR C
JR NZ, M2
LD A, # 7F
IN A, (# FE)
RRCA
JR C, M1
EI
RET
After that probe # 1 checks the presence of gating pulses at
a frequency about 2 Hz at 15, 14, 13, 12, 11, 10, 9 and
7 feet extra. ID7 (15 foot meets
Port # 0F, 14 - # 1F, etc).
1.6.1 (n) .2 See p.1.6.1 (a) .2
1.7 Checking the CAP is completed. Additional m / s 555ID7
can unsolder. For a final check of the quality of sound, run
what some prog to SOUND DRIVE, for example FLASH TRAKER, before
you start you have to remember in the corresponding ports (OUT
47, 63: OUT 63, 1963: OUT 111, 63: OUT 127, 63) to set the
volume.
2. Setting driving generators
02.01 soldered chip DD1, DD4.1
DD4.2.
2.2 (a) program is dialing test ports:
PORT EQU # FC77; # FD77; # FE77; # FF77
DI
M1 LD BC, PORT
OUT (C), A
LD A, # 7F
IN A, (# FE)
RRCA
JR C, M1
EI
RET
After that, checked the pulse of this form here: the often
that about 77 kHz at 15, 14, 13, 12 feet
DD1 (15 foot meets the port # FC77, 14
# FD77, etc.).
2.2 (n) are typed testing program port:
PORT EQU # FC77; # FD77; # FE77; # FF77
DI
M1 LD BC, PORT
OUT (C), A
LD BC, 0
M2 DEC BC
LD A, B
OR C
JR NZ, M2
LD A, # 7F
IN A, (# FE)
RRCA
JR C, M1
EI
RET
After that it checks for gating pulses at a frequency of
about 2 Hz at 15, 14, 13, 12 feet DD1 (15 foot meets the port #
FC77, 1914 - # FD77, etc).
02.03 soldered chip DD10, DD11
CLK signal is taken at the Pentagon with the 8D1. This
clock frequency which is usually 3.5MGts
served on the Z80, but if you have a turbo, then take it
directly from the processor can not. CLK2 signal is taken at
the Pentagon with 11D2. This clock frequency of 1.75 MHz, which
is fed to AY8910 (12) and its can be taken directly to the AY.
2.4 typed program:
10 LET R = 64887, 64887, 64887, 65143;
65143, 65143
20 LET P = 15735, 32119, 48503, 15991;
32375, 48759;
30 LET C = 52, 116, 180, 52, 116, 180;
1940 LET F = 1000: LET FH = INT (F/256): LET
FL = F-256 * FH
50 OUT R, C: OUT P, FL: OUT P, FH
60 PRINT AT 0,0; IN (P) +256 * IN (P),
70 GOTO 60
After you run the numbers should zamelkat
from 0 to 1000 in complete disarray, but very
quickly, and the findings of 10, 13, 17 and DD10
DD11 pulses must be received here this
forms: with a frequency of about 3.5
kHz at 10 and 13 feet, and 1.75 kHz at 17
legs (10DD10 corresponds to the first set
parameters, 13DD10 - second, 17DD10 - 3rd,
10DD11 - 4th, 13DD11 - 5th and 17DD11 - 6th).
2.5 If you then run 580VI53
test program should NOT turbo,
but better use of foreign analogues
8253 (82C53, D8253, etc.), which works perfectly normal and
turbo.
2.6 If the test is not, then you need to dial a test program
from the 2.2 port test should be:
PORT EQU # 3D77; # 7D77; # BD77; # FD77;
# 3E77; # 7E77; # BE77; # FE77
And then checked the gate. pulses at 21 feet DD10 and DD11
(ports # XD77 meets 21DD10, # XE77 21DD11
(X - any digit)).
3. Setting up the DMA controller
03.01 soldered chip DD3 (except 2
and 3 feet), DD4.4, DD5.1 - DD5.5, DD6, DD7,
DD14, between 36 feet DD6 (EOP) and +5 hangs resistor 10K.
____ __ __ _____ _____ ___
3.2 Signals MREQ, RD, WR, BUSAC, BUSRQ, RES
taken from 19, 21, 22, 23, 25 and 26 feet
processor, respectively.
3.3 typed test program:
10 LET P = 3191, 7287, 11383, 15479;
19575, 23671, 27767, 31863
20 FOR I = 0 TO 65535
1940 LET H = INT (I/256): LET L = I-H * 256
50 OUT P, L: OUT P, H
60 PRINT I, IN (P) +256 * IN (P)
70 NEXT I
Once launched, the screen should appear in two columns of
numbers, numbers in both columns must match. If the number is
in the right column does not change, then see 3.3.1, if the
numbers do not match, but in the right column numbers change,
you should check Conclusions 21 - 23, 26 - 30 DD6, and if there
order - to replace the DD6.
3.3.1 you need to dial a test program from the 2.2 port for
testing must be:
PORT EQU # 0C77; # 1C77; # 2C77; # 3C77;
# 4C77; # 5C77; # 6C77; # 7C77
And check for a signal sample at
11DD6 and 4DD6 (all ports). Must
check 13DD6 (normally there should be
log. 0).
3.4 typed test program:
1910 DATA 3191,7287,11383,15479,19575,
23671,27767,31863
20 FOR I = 0 TO 7
40 READ P
50 OUT P, I * 2: OUT P, I * 2 +1
60 PRINT I * 2: PRINT I * 2 +1
70 NEXT I
80 RESTORE
90 FOR I = 0 TO 7
100 READ P
110 PRINT AT I * 2,16; IN (P)
120 PRINT AT I * 2 +1,16; IN (P)
130 NEXT I
As before, the numbers in both columns
should coincide. If not,
then
3.4.1 Connecting the Probe # 2: probe "C"
to 11DD6, feelers "1", "2", "3", "4" to 32,
33, 34 and 35 feet DD6 respectively. Recruit program:
10 LET P = 3191, 7287, 11383, 15479;
19575, 23671, 27767, 31863
20 OUT P, 0
Once launched, the signature should be:
YYYY; NGGG; GNGG; NNGG;
GGNG; NGNG; GNNG; NNNG;
(Port 3191 sootv.signatura "YYYY", etc.)
3.5 Check now mode DMA. Recruit program:
TimerC EQU # FD77; # FD77; # FE77; # FE77
TimerD EQU # 3D77; # 7D77; # 3E77; # 7E77
TimerB EQU # 34, # 74, # 34, # 74
DmaS EQU # 0C77; # 2C77; # 4C77; # 6C77
DmaL EQU # 1C77; # 3C77; # 5C77; # 6C77
DmaC EQU # 50, # 51, # 52, # 53
DmaM EQU # 00; # 01, # 02, # 03
LD BC, TimerC
LD A, TimerB
OUT (C), A
LD BC, TimerD
LD DE, 2
OUT (C), E
OUT (C), D
LD BC, # 8C77
XOR A
OUT (C), A
LD BC, # CC77
OUT (C), A
LD BC, # BC77
LD A, DmaC
OUT (C), A
LD BC, DmaS
LD DE, # 8000
OUT (C), E
OUT (C), D
LD BC, DmaL
LD DE, 0
OUT (C), E
OUT (C), D
LD BC, # AC77
LD A, DmaM
OUT (C), A
RET
After starting the program performance
the computer is reduced by half. This
Test mode DMA. In this mode, is formed only by direct request
to access, and sample signals are not generated. Therefore,
the only visible effect - it's slowing down your computer due
to the fact that the DMA makes 437,500 memory accesses per
second (In test mode). Test mode is
and, after returning from a test program -
prior to discharge. Team OUT 56439, 0 (OUT
# DF77, # 00) also resets the controller
DMA, after her performance should return to normal. Your
computer must steadily work in the test. The main disease -
malfunction in RAM due to poor contact between chip socket and
inaccurate signal phase CAS. The Pentagon helps Installation
extra. Capacitor 20 - 40 pF between 3DD45 and land, but it is
best to remake addressing memory, do not be afraid to do this
swap 2 pairs of signals. For the rest of the computers do not
need this. This is due to the extremely long
regeneration cycle of memory, and wedging
DMA requests to the memory of all stretches
him.
3.5.1 If the test did not go (no slowdown there), then you
would enter the program from § 3.5, change in her line:
DmaC EQU # 40, # 41, # 42, # 43
After starting the test - on the withdrawal 4DD14;
7DD14; 9DD14; 13DD14 (19DD6; 18DD6; 17DD6;
16DD6) should be a log. 1, if it is not there
you should check the output 25DD6; 26DD6;
27DD6; 28DD6 there must also be a log. 1,
if its not there, then the fault DD6, otherwise
oscilloscope to check the pulse of this form here: the cha
quency 1.75MGts at pin 2i3DD14; 6DD14;
11i12DD14; 15DD14 or connect to it
Probe # 1 - its LED will glow in polnakala. If there are no
impulses, the relationship nepropayana DD10 (DD11) - DD14, if
is - that is defective DD14.
Bits 4 - 7 Status Register (# 8C77
(35959)) must have the same value that
and conclusions 19 - 16 DD6 (concluded in 1919 resp.
bit 4 pin. 18 - bit 5, etc.), ie, if the output log. 0 then acc
bit = 0 and vice versa. This is also helpful to be sure.
3.5.2 If in the previous paragraph it's OK,
and the test anyway is not, check the bus request signals:
3.5.2 (a) program is dialing out
clause 3.5. At 10DD6 need an oscilloscope to verify the
presence of pulses of this form here:
frequency 440kGts. At 8DD5 and
25Z80 to be impulses
this form: with the same-chastot8oy.
3.5.2 (n) are typed program:
TimerC EQU # FD77; # FD77; # FE77; # FE77
TimerD EQU # 3D77; # 7D77; # 3E77; # 7E77
TimerB EQU # 34, # 74, # 34, # 74
DmaS EQU # 0C77; # 2C77; # 4C77; # 6C77
DmaL EQU # 1C77; # 3C77; # 5C77; # 6C77
DmaC EQU # 40, # 41, # 42, # 43
DmaM EQU # 00; # 01, # 02, # 03
LD BC, TimerC
LD A, TimerB
OUT (C), A
LD BC, TimerD
LD DE, 2
OUT (C), E
OUT (C), D
LD BC, # 8C77
XOR A
OUT (C), A
LD BC, # CC77
OUT (C), A
LD BC, # BC77
LD A, DmaC
OUT (C), A
LD BC, DmaS
LD DE, # 8000
OUT (C), E
OUT (C), D
LD BC, DmaL
LD DE, 0
OUT (C), E
OUT (C), D
M1 LD BC, # AC77
LD A, DmaM
OUT (C), A
M2 HALT
HALT
HALT
HALT
HALT
LD A, # 7F
IN A, (# FE)
RRCA
JR C, M2
RRCA
JR C, M1
RET
After a set of programs to be connected to the probe # 1
8DD5. At each press SPACE LED probe should change
its state to the contrary. Exit
from the program SS + SPACE. If all goes well,
then checked 8DD5 and 25Z80.
3.5.3. If running
of clause 3.5. and p.3.5.1 computer freezes, and the
25Z80 constantly log. 0 - check
line prompted the bus. Check 4DD5 - there should be a log. 1.
If all so it is - failure DD6.
3.5.4. To verify that the final controller DMA use the tool
FreeSpeed.
3.6. Soldered chip DD2, DD8.1,
DD8.4, DD9, DD12 and DD13.
3.6.1 Now you need to do the most
Nasty operation - changes to board
computer. Unpleasant because, although
Many companies are proud of their "system
tires, which are like-how derived
signals for direct access, unfortunately
there is no computer that can
without alterations to provide for direct
access more than 48k of memory. So I allow myself to make a
digression to somehow explain what to do, since the
instructions like "Take it, soldered in." I can give only a
very limited number of schemes.
So, a little bit about how computer memory addresses. For
this it has a thing as a memory manager. Its main
task - to take the address from the processor and
convert it to the IC
memory. First, consider the simplest
manager - such as standing in the 48m computer. Some people say
that there is no 48m Manager .. and wrong. Manager there, but
very small vermillion. The only thing he does is check that the
A14 and A15 are equal to 0, and if so, sends
address in ROM to RAM differently. Quite simply,
but if such a computer is assembled on 565RU5,
capacity of which 64KB, then in this scenario 16kbayt, wasted
(covered PZUhoy).
Now we'll see what happens in the 128M.
Here the picture is more complicated. The processor is not
can address more than 65536 (2 ^ 16)
bytes because it has only 16 address
lines. For this manager does the following. When the processor
accesses the address # C000-# FFFF (ie, A14 and A15 = 1) the
manager does not give significant bits of the address right in
RAM, and replace them with values from the port # 7FFD.
Denote the highest address that go to the RAM as A14 ', A15',
A16 '(and the A17', A18 'for 512K) to distinguish them from the
processor (A0-A13 go directly to the RAM). Now look what
happens when CPU accesses to different sites
Memory:
Range A14 A15 A14 'A15' A16 '
# C000-# F000 January 1 is taken from # 7FFD
# 8000 - # BFFF 0 1 0 1 0
# 4000 - # 7FFF 1 0 1 0 1
# 0000 - # 3FFF 0 0 RAM not selected
For 512y machines are absolutely the same thing only added
two more targeted line of A17 'and A18'.
All of this somehow works yet
DMA access, but for DMA
Such a structure of memory quite good. First controller DMA - it
almost coprocessor, he, unlike other
peripheral controllers can address
memory instead of the processor, but he chooses
out only the data it receives commands
through the port. Therefore, it is not completely necessary ROM
address space is very difficult to imagine why you need direct
access to the ROM. Secondly it is absolutely impossible switch
port # 7FFD so that each Channel grabs data from your page.
And thirdly, it is not difficult to see the processor page size
have 16k, but DMA controller can transmit at a time until
64k, which makes tools to 4 times longer.
From all the above it follows that
be found in older computer address
line RAM A14 ', A15', A16 '(and the A17', A18 '
to 512K) and make sure that they are turned off by an external
signal. All anything, but Here are just a manager almost always
scattered through the board and the scheme. Specific schemes
connect to two prominent my dispatchers RAM 512k will be given
in the following times. Connecting to the Pentagon 128k here
is: The signal A16 'is connected to the 9D61, A15' - 7D61, A14
'- 4D61, nothing has been cut off, 15D61 except on the ground.
At 15D61 connects AEN (not inverted). Note: if You 512K or
above, I recommend first connect the card with no alteration
Manager memory as 128k. Then, making sure that
the card works normally produce alteration Manager.
3.7. Assembling the controller interrupt does not cause any
difficulties. After final assembly manager to cut a path that
goes to the output INT Z80. Signal INT, which came on the
processor is connected to the signal INT on the map, and INT
'with maps supplied to the Z80. Manager Works
Interrupts can check utility INT.
Final inspection of assembly maps
can be produced using the programs
MODPlayer, SFX, etc.
Used m / s:
555ID7 - 2 pcs
555LP8 - 1 pc
555LI1 - 2 pcs
555LN1 - 1 pc
1810VT37 - 1 pc
555AP4 - 1 pc
555LA3 - 1 pc
555IR26 - 1 pc
580VI53 - 2 pcs
555LL1 - 2 pcs
555IR22 - 2 pcs
555TR2 - 2 pcs
555TM2 - 1 pc
555TM8 - 1 pc
555IR23 - 4 pieces
555TM9 - 4 pieces
572PA1 - 8
KR140UD20 - 4 pieces
Application. Logichekie probes
Probe # 1.
LED strobe pulses.
1 5 / / 560th
Probe +5 <R Q> +5 B
3 AL307
+5 B
4 5 "2" / /
"2" +5 B
June 7, "3" / /
"3" +5 B
September 8 "4" / /
"4" +5 B
December 13 '5 "/ /
"5" +5 B
14 15 '6 "/ /
"6" +5 B
17 16 '7 "/ /
"7" +5 B
18 19 '8 "/ /
"8" +5 B
11 __ 1
"C"
