(C) 2oo2 Disabler /
DPL
Today we'll talk about static memory, or rather it is
connected. As I hope you understand we are talking about the
cache. Without the cache to work pretty napryazhno! In it you
can shove commander and reset the buttons fall out with him.
You can stuff a lot of things, but it all depends on the amount
of cache. I think that we should not talk about connecting 16kb
- this is not enough. We'll talk about 32kb, 64kb or more (up
to 256kb).
Consider a variant of "32kb". In the zero-half we service
prog, the first commander. Load mod_play and he kills commander
or service, or both! Alternatively, you can make a
write-protect the cache. Made it easy! Cut the WR signal from
the cache and set the switch:
wr
> _____ 27.Cashe
+5 V
>
But this option is not without flaws. For example, should run
cp / m. Without the cache, it will not work! The solution is
obvious: put a 64kb cache!
A bit of theory: the cache is activated when reading from the
port # fb, and shuts down when reading from the port # 7b. When
you turn the cache is substitution ROM cache. As is known, can
be simultaneously connected only 16kb ROM, and therefore 16kb
cache. According to this cache paginated by 16kb. In the
version of "32kb" cache Rugs switched so as ROM and halves, ie,
with the fourth bit of port # fd. In the version of "64kb"
there is a problem half of the sample cache. Alternatively, you
can use a free three bits of the port # fe (seventh to fifth).
They allow you to connect up to 256kb cache!
So the essence of refinement is this: we have two chips on
32kb. Entry into one of them is always possible, and the second
is the write protection (see above). In normal operation, the
computer is always turned on the first of the chips (one that
is not write-protected). Button on the NMI or Reset (someone
like) included the second half. Okay, enough theory. Now the
practice:
act - the cache enable signal (nmi / reset)
sel - sample signal chip cache (20/22 pin cache)
sel # fe - sample signal port # fe. The Pentagon - 9.D43
Taganrog - 9.D42
1k
+5 V> RQ a> 22.Cashe1
D5> D sel>> 20.Cashe1
sel # fe> C _
act> S Q> 22.Cashe2
1> 20.Cashe2
Products: 555TM2, 555LL1
PS: 64kb revision before going on the basis of 32kb.
Hedgehog-whether that - write ...
